EPM5128JC-2 vs EPM5128JC-1 比較
詳細並排比較 EPM5128JC-2 由 Altera 與 EPM5128JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128JC-2 | EPM5128JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | Erasable Programmable Logic Device (EPLD/CPLD) |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 45 ns (max) | — |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | — |
| 封裝 | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| 供應電壓 | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| RoHS 狀態 | Non-compliant (ceramic windowed package contains lead-bearing solder) | non_compliant (ceramic windowed package) |
| Logic Family | TTL-compatible I/O | — |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | — | 62.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |
| 生命週期狀態 | — | Obsolete - last-time-buy inventory only |