EPM51929C vs EPM5192AGC 比較

詳細並排比較 EPM51929C 由 Intel 與 EPM5192AGC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM51929C EPM5192AGC
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable / OTP Complex PLD (EPLD)
Architecture Multi-array matrix (PAL-based macrocells) CMOS, sum-of-products with macrocell output logic
Logic Density [DATA_NEEDED: usable gates] High-density (per MAX 5000 family definition)
Number of Macrocells [DATA_NEEDED: macrocell count] —
腳位數 [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
工作溫度 Commercial (0C to +70C) [DATA_NEEDED: operating temperature range]
供應電壓 [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC nominal and tolerance]
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
安裝類型 Surface Mount or Through-Hole (package dependent) Through-hole (Pin Grid Array)
RoHS 狀態 unknown Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Lead-Free unknown —
MSL 等級 [DATA_NEEDED] —
Family — MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Macrocells — 192
Process Technology — CMOS
封裝 — 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

資料表與資源

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