EPM5192AGC-15 vs EPM5192AGC84-15 比較
詳細並排比較 EPM5192AGC-15 由 Altera 與 EPM5192AGC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AGC-15 | EPM5192AGC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 15 ns |
| Supply Voltage (VCC) | 5 V | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | Ceramic Pin Grid Array (PGA) | 84-pin Ceramic PGA (Pin Grid Array) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| 生命週期狀態 | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable/OTP Complex PLD |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Process Technology | — | CMOS |
| Programmable Element | — | UV-Erasable EPROM cell |
| 安裝類型 | — | Through-Hole |