EPM5192AGC-15 vs EPM5192AQC-2 比較
詳細並排比較 EPM5192AGC-15 由 Altera 與 EPM5192AQC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AGC-15 | EPM5192AQC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | MAX 5000 (EPM5192) |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | 72 |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 45 ns (-2 speed grade) |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | Ceramic Pin Grid Array (PGA) | 100-pin PQFP (R-PQFP-G100) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial / industrial / military grade] |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: confirmed compliance status] |
| 生命週期狀態 | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| User I/O Pins | — | 64 |
| 最大時脈頻率 | — | [DATA_NEEDED: max fMAX for -2 grade] |
| Process Technology | — | CMOS |
| Switch Matrix | — | UV-Erasable / OTP (windowless on AQC package) |
| Lead Pitch | — | 0.635 mm |
| Terminal Form | — | Gull-wing |
| 安裝類型 | — | Surface Mount |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary scan |