EPM5192AGC vs EPM5192AGC-15 比較

詳細並排比較 EPM5192AGC 由 Altera 與 EPM5192AGC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192AGC EPM5192AGC-15
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) —
Device Type UV-Erasable / OTP Complex PLD (EPLD) —
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
封裝 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) Ceramic Pin Grid Array (PGA)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
工作溫度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
供應電壓 [DATA_NEEDED: VCC nominal and tolerance] —
安裝類型 Through-hole (Pin Grid Array) —
RoHS 狀態 Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Product Type — EPLD (Erasable Programmable Logic Device)
Series — MAX 5000
Logic Array Blocks — 16 (typical for 192-macrocell MAX 5000)
Maximum User I/O Pins — 64
Dedicated Inputs — 7
Total Inputs — 72
Propagation Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Supply Voltage (VCC) — 5 V
Technology — CMOS, UV-erasable EPROM
Programming Method — UV erase + EPROM program (via Altera programmer)
生命週期狀態 — Obsolete / Last Time Buy (per Altera legacy product list)

資料表與資源

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