EPM5192AJC-25 vs EPM5192AGC 比較
詳細並排比較 EPM5192AJC-25 由 Altera 與 EPM5192AGC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AJC-25 | EPM5192AGC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| 封裝 | PLCC-68 (windowed ceramic, AJC) | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| 腳位數 | 68 | — |
| 安裝類型 | Surface Mount | Through-hole (Pin Grid Array) |
| 供應電壓 | 5 V (typical) | [DATA_NEEDED: VCC nominal and tolerance] |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| 工作溫度 | [DATA_NEEDED: exact operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | UV-Erasable / OTP Complex PLD (EPLD) |
| Logic Density | — | High-density (per MAX 5000 family definition) |
| Architecture | — | CMOS, sum-of-products with macrocell output logic |
| Process Technology | — | CMOS |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Programmability | — | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |