EPM5192AQC-2 vs EPM5192AGC-15 比較
詳細並排比較 EPM5192AQC-2 由 Altera 與 EPM5192AGC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AQC-2 | EPM5192AGC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | — |
| Series | MAX 5000 (EPM5192) | MAX 5000 |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | 72 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 15 ns (pin-to-pin, -15 speed grade) |
| 最大時脈頻率 | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | — |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| 封裝 | 100-pin PQFP (R-PQFP-G100) | Ceramic Pin Grid Array (PGA) |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| 工作溫度 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| 安裝類型 | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | — |
| RoHS 狀態 | [DATA_NEEDED: confirmed compliance status] | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| 生命週期狀態 | — | Obsolete / Last Time Buy (per Altera legacy product list) |