EPM5192GC-1 vs EPM5192AGC 比較
詳細並排比較 EPM5192GC-1 由 Altera 與 EPM5192AGC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GC-1 | EPM5192AGC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Classic) | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3,750 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Process Technology | CMOS, UV-erasable / OTP | CMOS |
| 封裝 | 100-pin Ceramic PGA (GC) | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| 安裝類型 | Through-Hole (PGA) | Through-hole (Pin Grid Array) |
| Configuration Method | UV-Erase / One-Time Programmable | — |
| Interconnect | Peripheral Interconnect Array (PIA) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Device Type | — | UV-Erasable / OTP Complex PLD (EPLD) |
| Logic Density | — | High-density (per MAX 5000 family definition) |
| Architecture | — | CMOS, sum-of-products with macrocell output logic |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Programmability | — | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal and tolerance] |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |