EPM5192GC1 vs EPM5192AGC 比較
詳細並排比較 EPM5192GC1 由 Altera 與 EPM5192AGC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GC1 | EPM5192AGC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable / OTP Complex PLD (EPLD) |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Programming Technology | UV-Erasable / OTP EPROM | — |
| Package Type | Ceramic PGA (Pin Grid Array) | — |
| Logic Elements | 192 macrocells with AND/OR array | — |
| Process Technology | EPROM-based CMOS | CMOS |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| 腳位數 | [DATA_NEEDED: pin count for GC1 PGA package] | — |
| 安裝類型 | Through-hole (PGA) | Through-hole (Pin Grid Array) |
| RoHS 狀態 | unknown | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Development Tool | Altera MAX+PLUS II | — |
| Macrocells | — | 192 |
| Logic Density | — | High-density (per MAX 5000 family definition) |
| Architecture | — | CMOS, sum-of-products with macrocell output logic |
| 封裝 | — | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Programmability | — | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal and tolerance] |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |