EPM5192GI vs EPM5130GI 比較
詳細並排比較 EPM5192GI 由 Altera 與 EPM5130GI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GI | EPM5130GI |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| Macrocells | 192 | 128 |
| Logic Array Blocks (LABs) | 16 (12 macrocells per LAB) | 8 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 19 |
| Total Inputs | 72 | 68 |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Internal Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| 工作溫度 | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Package Type | 84-pin PGA (Pin Grid Array), ceramic with quartz window | — |
| Programmable | UV-erasable (windowed) and OTP variants | — |
| 安裝類型 | Through-hole (PGA) | — |
| RoHS 狀態 | [DATA_NEEDED: not confirmed in verified web data] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| I/O Pins | — | 48 |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Process Technology | — | CMOS |
| 供應電壓 | — | 5 V |
| 封裝 | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |