EPM5192GM-1 vs EPM5192JM 比較
詳細並排比較 EPM5192GM-1 由 Altera 與 EPM5192JM 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GM-1 | EPM5192JM |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Logic Cells | 192 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmable Element | UV-erasable EPROM | — |
| 封裝 | CPGA-84 (Windowed Ceramic PGA) | 84-pin Ceramic JLCC with quartz window (J84) |
| 腳位數 | 84 | — |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | — |
| 工作溫度範圍 | [DATA_NEEDED: commercial/industrial/military grade] | -55 C to +125 C (military grade, 'M' suffix) |
| Programmable Macrocells | 192 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| 安裝類型 | Through-Hole (Pin Grid Array socket) | — |
| RoHS Compliance | unknown (legacy ceramic PGA) | — |
| Lead-Free Status | unknown | — |
| Programming Interface | Altera ByteBlaster / JEDEC bitstream | — |
| Development Tool | Altera MAX+PLUS II (legacy) | MAX+PLUS II (legacy Altera toolchain) |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 192 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Input Channels | — | 72 |
| Propagation Delay (tPD) | — | 55 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Technology | — | CMOS, UV-erasable |
| Logic Architecture | — | Shared product-term AND/OR, programmable polarity |
| Programming Method | — | UV erase + EPROM programmer, JEDEC map |
| Compliance | — | MIL-STD-883 processing available on /883B suffix variants |