EPM5192GM vs EPM5192GM-2 比較

詳細並排比較 EPM5192GM 由 Altera 與 EPM5192GM-2 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192GM EPM5192GM-2
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (PLD) EPLD (Erasable Programmable Logic Device)
Technology CMOS —
Number of Macrocells 192 —
Usable Gates 3,750 —
Pin-to-Pin Delay (tPD) 15 ns (fastest speed grade); 55 ns (this part) —
Counter Frequency (fCNT) up to 76.9 MHz —
Propagation Delay (tPD, this part) 55 ns —
封裝 CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) PGA-84 (Ceramic Pin Grid Array, windowed)
安裝類型 Through-Hole (PGA) Through-hole (PGA socket)
Erasure Method UV (windowed ceramic package) —
供應電壓 [DATA_NEEDED: typical VCC range] [DATA_NEEDED: VCC nominal, typically 5 V for MAX 5000]
Maximum User I/O [DATA_NEEDED: exact I/O count for CPGA-84] —
工作溫度 [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: military/industrial grade temperature range]
RoHS 狀態 Non-compliant (contains lead in ceramic PGA) [DATA_NEEDED: ceramic PGA with UV window is typically non-RoHS - verify with manufacturer]
Process Node [DATA_NEEDED: CMOS process geometry] —
Programming Interface JTAG-compatible (per MAX 5000 family) —
Family — Altera MAX 5000
Macrocell Count — 192
Logic Elements — [DATA_NEEDED: logic element count for MAX 5000 family]
Propagation Delay (tPD) — 55 ns
Speed Grade — -2
Process Technology — CMOS
Programmability — UV-erasable (windowed package)
腳位數 — 84
Datasheet Page Count — 52

資料表與資源

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