EPM5192JC-ES vs EPM5192GI 比較
詳細並排比較 EPM5192JC-ES 由 Intel 與 EPM5192GI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-ES | EPM5192GI |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 16 (12 macrocells per LAB) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| 封裝 | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | — |
| 安裝類型 | Surface Mount | Through-hole (PGA) |
| Technology | CMOS | CMOS EPROM (UV-erasable / OTP) |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range for ES grade] | -40 C to +85 C (Industrial) |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | 64 |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not confirmed in verified web data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 55 ns |
| Maximum Internal Frequency (fCNT) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Package Type | — | 84-pin PGA (Pin Grid Array), ceramic with quartz window |
| Programmable | — | UV-erasable (windowed) and OTP variants |