EPM5192JI vs EPM5192JC 比較
詳細並排比較 EPM5192JI 由 Altera 與 EPM5192JC 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JI | EPM5192JC |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tpd) | 55 ns | — |
| 供應電壓 | 4.75 V to 5.25 V (nominal 5 V) | [DATA_NEEDED: VCC nominal] |
| Technology | CMOS EPROM, UV-erasable | — |
| 封裝 | 84-pin PLCC (windowed, J-suffix ceramic) | 68-pin PLCC (JC) windowed ceramic |
| 工作溫度 | -40 C to +125 C (industrial, I-suffix) | [DATA_NEEDED: commercial / industrial / military grade] |
| 安裝類型 | Surface Mount (PLCC socket recommended for UV erasure) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | [DATA_NEEDED: original Altera marking not RoHS] |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | UV-erase + EPROM programmer |
| Erasure Method | UV exposure through windowed package | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |