EPM5192LC vs EPM5192GM 比較
詳細並排比較 EPM5192LC 由 Altera 與 EPM5192GM 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC | EPM5192GM |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Global Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | — |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | JTAG-compatible (per MAX 5000 family) |
| Operating Temperature (commercial) | 0C to +70C | — |
| 封裝 | JLCC-68 (windowed ceramic, LC suffix) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| 安裝類型 | Surface Mount | Through-Hole (PGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in ceramic PGA) |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (PLD) |
| Technology | — | CMOS |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| 供應電壓 | — | [DATA_NEEDED: typical VCC range] |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| 工作溫度 | — | [DATA_NEEDED: commercial/industrial/military grade] |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |