EPM5192LC1 vs EPM5192JC84-1 比較
詳細並排比較 EPM5192LC1 由 Altera 與 EPM5192JC84-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC1 | EPM5192JC84-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | UV-Erasable/OTP Complex Programmable Logic Device (CPLD) |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| 封裝 | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| 最大時脈頻率 | 50 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| JEDEC Package Code | S-PQCC-J84 | — |
| Propagation Delay (tpd) | — | 40 ns (worst case) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V ±5 %) |
| Operating Temperature Grade | — | Commercial |
| JESD-30 Package Code | — | S-CQCC-J84 |
| Terminal Form | — | J-BEND |
| Package Shape | — | SQUARE |
| Programmability | — | UV-erasable (window) / OTP in production |
| Configuration Memory | — | EPROM (non-volatile, instant-on) |