EPM5192LC2 vs EPM5192LC-2N 比較
詳細並排比較 EPM5192LC2 由 Intel 與 EPM5192LC-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC2 | EPM5192LC-2N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tpd) | 45 ns (LC-2 speed grade) | — |
| 最大時脈頻率 | 50 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS | — |
| 封裝 | PQCC-84 (84-pin Plastic J-Lead Chip Carrier) | — |
| 安裝類型 | Surface Mount | Surface Mount (LC package) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Reprogrammability | Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic) | — |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Package Type | — | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Speed Grade | — | -2 (tPD approximately 25 ns) |
| Propagation Delay (typical) | — | 25 ns |
| 供應電壓 | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| RoHS 狀態 | — | Compliant (per -N lead-free suffix) |
| Lead-Free | — | Yes (per -N suffix) |
| Architecture | — | Programmable Logic Array (PLA) with global PIA |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |