EPM570F100C4N vs EPM570GF100C5N 比較

詳細並排比較 EPM570F100C4N 由 Intel 與 EPM570GF100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM570F100C4N EPM570F100C4N - MAX II CPLD, 440 LEs, 100-FBGA | Intel

EPM570F100C4N - MAX II CPLD, 440 LEs, 100-FBGA | Intel

EPM570F100C4N ✓ 啟用中
Altera
EPM570GF100C5N EPM570GF100C5N - MAX II 570 LE CPLD, 100-FBGA | Altera

EPM570GF100C5N - MAX II 570 LE CPLD, 100-FBGA | Altera

EPM570GF100C5N ✓ 啟用中

規格比較

參數 EPM570F100C4N EPM570GF100C5N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II —
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements 440 LE 570
Macrocells 440 440
Maximum User I/O 80 —
Pin-to-Pin Delay (tPD1) 5.4 ns —
User Flash Memory 4.4 Kbits —
Configuration Technology Flash (non-volatile, instant-on) —
Operating Voltage (Core) 3.3 V (internal regulator) —
I/O Voltage Support (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
封裝 100-FBGA (FineLine BGA) 11 mm x 11 mm 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch
工作溫度 0 C to +85 C (commercial) -40C to +125C (industrial)
安裝類型 Surface Mount (BGA) Surface Mount
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Hot Socketing Yes —
Device Family — MAX II
User I/Os — 76
Propagation Delay (tPD) — 5.4 ns
Configuration Memory — On-chip Flash (non-volatile)
Core Voltage — 1.8 V (internal)
I/O Voltage Support — 1.8 V / 2.5 V / 3.3 V (5.0 V tolerant inputs)
Programming Interface — IEEE 1532 / JTAG (IEEE 1149.1) ISP
RoHS 狀態 — Compliant (lead-free)
Logic Family / Process — CMOS, Flash-based LUT
LABs — 4 (16 macrocells per LAB)

資料表與資源

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