EPM7096LC84-10 vs EPM7096LC84-15 比較
詳細並排比較 EPM7096LC84-10 由 Intel 與 EPM7096LC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7096LC84-10 | EPM7096LC84-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 96 | — |
| Logic Array Blocks (LABs) | 4 | 4 |
| Maximum User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| 封裝 | 84-PLCC (J-Lead) | — |
| Process Technology | EEPROM-based, 5.0 V low-power CMOS (L) | — |
| Supply Voltage (VCC) | 5.0 V nominal (4.75 V - 5.25 V) | 4.75 V to 5.25 V |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| MultiVolt I/O | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface | — |
| 工作溫度範圍 | 0C to +70C (Commercial, 'C') | — |
| Configuration Memory | Non-volatile EEPROM (instant-on) | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| 安裝類型 | Surface Mount (PLCC socket or SMT) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Usable Gates | — | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| User I/O Pins | — | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| 工作溫度 | — | 0C to +70C (commercial) |
| 封裝 / 外殼 | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |