EPM7096LC84-10 vs EPM7096LC84-15 Comparison

Detailed side-by-side comparison of EPM7096LC84-10 by Intel and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7096LC84-10 EPM7096LC84-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.10 $9.85
Family MAX 7000 MAX 7000
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 96 β€”
Logic Array Blocks (LABs) 4 4
Maximum User I/O Pins 36 β€”
Propagation Delay (tPD) 10 ns (-10 speed grade) β€”
Package 84-PLCC (J-Lead) β€”
Process Technology EEPROM-based, 5.0 V low-power CMOS (L) β€”
Supply Voltage (VCC) 5.0 V nominal (4.75 V - 5.25 V) 4.75 V to 5.25 V
In-System Programmability Yes, via IEEE 1149.1 JTAG β€”
MultiVolt I/O 2.5 V / 3.3 V / 5.0 V mixed-voltage interface β€”
Operating Temperature Range 0C to +70C (Commercial, 'C') β€”
Configuration Memory Non-volatile EEPROM (instant-on) β€”
Programmable Interconnect PIA (Programmable Interconnect Array) β€”
Mounting Type Surface Mount (PLCC socket or SMT) Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Series β€” MAX 7000 (second-generation MAX architecture)
Macro Cells β€” 96
Usable Gates β€” 1,800
Pin-to-Pin Propagation Delay (tPD) β€” 15 ns
Maximum Operating Frequency β€” 76.9 MHz
User I/O Pins β€” 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split])
Programmable Type β€” EE PLD (in-system programmable via JTAG)
Programming Interface β€” IEEE Std. 1149.1 JTAG
Operating Temperature β€” 0C to +70C (commercial)
Package / Case β€” 84-PLCC (J-Lead)
Supplier Device Package β€” 84-PLCC (29.31 x 29.31 mm)
Data Retention β€” [DATA_NEEDED: data retention years]
Erase/Program Endurance β€” [DATA_NEEDED: erase/program cycle count]

Datasheets & Resources

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