EPM7128SLC8410 vs EPM7128ELC84-12 比較

詳細並排比較 EPM7128SLC8410 由 Intel 與 EPM7128ELC84-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM7128SLC8410 EPM7128ELC84-12
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000S MAX 7000 (MAX 7000E series)
Macrocells 128 128
Logic Elements / Gates 2500 usable gates —
User I/O Pins 68 —
Number of Logic Array Blocks (LABs) 8 —
Propagation Delay (tPD) 10 ns —
Setup Time (tSU) 7 ns —
Maximum Operating Frequency 125 MHz (counter) —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5 V nominal) —
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V —
Program Memory Type EEPROM (in-system programmable) —
JTAG Support IEEE Std 1149.1 boundary-scan —
封裝 84-pin PLCC (J-lead) 84-pin PLCC (J-Lead, QCCJ)
工作溫度 0C to +70C (commercial) 0C to +70C (commercial)
安裝類型 Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket compatible)
RoHS 狀態 [DATA_NEEDED: RoHS status - not stated in verified data] Non-compliant (legacy 5V part, SnPb finish)
Logic Family — CMOS, EEPROM-based
Usable Gates — 2,500
Logic Array Blocks (LABs) — 8
User I/Os — 84
Propagation Delay (tpd1) — 12 ns
Internal Global Clock Frequency — 90.9 MHz
Setup Time — 4.5 ns
Supply Voltage (VCCINT / VCCIO) — 5 V (4.75 V to 5.25 V)
Programming Interface — JTAG (IEEE 1149.1) / ISP
腳位數 — 84

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