EPM7160SLC84-10 vs EPM7160SLC84-15 比較
詳細並排比較 EPM7160SLC84-10 由 Altera 與 EPM7160SLC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160SLC84-10 | EPM7160SLC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 64 | 64 |
| Usable Gates | 3,200 | 3,200 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | — |
| Technology | EEPROM-based CMOS | CMOS, EEPROM configuration |
| 封裝 | 84-Pin PLCC (J-Lead) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| 工作溫度 | 0C to +70C (Commercial) | 0 C to 70 C |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Not RoHS compliant (contains lead, SnPb finish typical) |
| Maximum Propagation Delay | — | 15 ns |
| Supply Voltage (VCCINT/VCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | — | Configurable 3.3 V or 5 V |
| Package Type | — | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) |
| Terminal Pitch | — | 1.270 mm |
| Programming Interface | — | JTAG (IEEE 1149.1) in-system programmable |
| Lifecycle | — | Obsolete / last-time-buy (per Altera/Intel PDN) |