EPM7160SQC160-10 vs EPM7160SQC160-7 比較
詳細並排比較 EPM7160SQC160-10 由 Altera 與 EPM7160SQC160-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 Obsolete規格比較
| 參數 | EPM7160SQC160-10 | EPM7160SQC160-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 160 | — |
| Logic Elements / Gates | 3,200 usable gates | — |
| User I/Os | 104 | — |
| Logic Array Blocks (LABs) | 10 | 10 |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage Tolerance | 5.0 V | — |
| Programming Technology | EEPROM, in-system programmable | — |
| JTAG Support | IEEE 1149.1 (boundary-scan + ISP) | — |
| 封裝 | PQFP-160 (SQC160) | 160-pin PQFP (BQFP, 28x28 mm) |
| 工作溫度 | 0 C to +70 C (commercial) | 0 °C to 70 °C (commercial) |
| Logic Family | CMOS | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM-based | — |
| RoHS 狀態 | unknown | Not Compliant (per Arrow listing) |
| Lead-Free | unknown | — |
| Macrocells | — | 160 |
| Usable System Gates | — | 3,200 |
| Product Terms per Macrocell | — | 32 |
| Maximum User I/Os | — | 104 |
| Global Clocks | — | 2 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Propagation Delay (tPD) | — | 7.5 ns |
| Program Memory Type | — | EEPROM (in-system programmable) |
| JTAG (IEEE 1149.1) | — | Yes (ISP via JTAG) |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| Part Status | — | Obsolete |