EPM7256SQC208-15 vs EPM7256SQI208-10 比較
詳細並排比較 EPM7256SQC208-15 由 Altera 與 EPM7256SQI208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256SQC208-15 | EPM7256SQI208-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 7000S | — |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | 5000 |
| User I/O Pins | 164 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| 工作溫度範圍 | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| 封裝 | 208-pin PQFP (28x28 mm) | 208-pin PQFP (QFP208) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| RoHS 狀態 | Contains lead / RoHS non-compliant (per third-party listing) | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Contains lead | — |
| Device Family | — | MAX 7000 (EPM7256) |
| Logic Array Blocks | — | 16 |
| Maximum User I/O Pins | — | 164 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage Range | — | 4.5 V to 5.5 V |
| Technology | — | CMOS EEPROM |
| In-System Programmable | — | Yes (IEEE 1149.1 JTAG) |
| Package Body Material | — | Plastic/Epoxy |
| Terminal Form | — | Gull Wing |
| JESD-30 Package Code | — | S-PQFP-G208 |
| JESD-609 Terminal Finish Code | — | E3 |