EPM7256SQC208-15N vs EPM7256SQC208-7N 比較
詳細並排比較 EPM7256SQC208-15N 由 Altera 與 EPM7256SQC208-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256SQC208-15N | EPM7256SQC208-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay | 15 ns (speed grade -15) | — |
| 供應電壓 | 5 V | — |
| 封裝 | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | IEEE 1149.1 boundary-scan | IEEE 1149.1 boundary-scan (ISP capable) |
| In-System Programmability | Yes (ISP) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| RoHS 狀態 | Lead free / RoHS Compliant | Compliant (N suffix = lead-free) |
| Logic Array Blocks | 16 macrocells per LAB | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Speed Grade | -15 | -7 (7.5 ns pin-to-pin) |
| Product Category | CPLD - Complex Programmable Logic Devices | — |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 5,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Open-Drain Output | — | Optional per I/O pin |