EPM9320LI84-20 vs EPM9560ELI84-20 比較
詳細並排比較 EPM9320LI84-20 由 Altera 與 EPM9560ELI84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
EPM9560ELI84-20 Obsolete規格比較
| 參數 | EPM9320LI84-20 | EPM9560ELI84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera (acquired by Intel) | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 560 |
| User I/Os | 60 | — |
| 封裝 | 84-PLCC (J-Lead, plastic LCC) | 84-pin PLCC |
| Propagation Delay (tPD) | 20 ns | — |
| Internal Frequency | 118 MHz | — |
| 供應電壓 | 5.0 V | — |
| Logic Family | CMOS, EEPROM-based | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) - EEPROM-based |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | 5.0 V ISP via IEEE 1149.1 JTAG |
| 工作溫度 | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| 安裝類型 | Surface Mount (PLCC socket-compatible) | Through-Hole / Socket |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Process Technology | High-performance CMOS EEPROM | CMOS EEPROM |
| Usable Gates | — | 6,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 212 (package-dependent) |
| Flip-Flops | — | 212 |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Speed Grade | — | -20 |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Standards | — | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |