EPM9400RC208-20 vs EPM9320RI208-20N 比較

詳細並排比較 EPM9400RC208-20 由 Altera 與 EPM9320RI208-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM9400RC208-20 EPM9320RI208-20N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family MAX 9000 —
Programmable Type In System Programmable (ISP) —
Macro Cells 400 —
Usable Gates 8,000 —
Pin-to-Pin Propagation Delay 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (Internal) 4.75 V to 5.25 V —
Configuration Technology EEPROM-based (non-volatile) —
JTAG Interface IEEE Std. 1149.1 IEEE Std. 1149.1 compliant
封裝 208-pin RQFP (28x28 mm) 208-pin PQFP (Plastic Quad Flat Pack)
Supplier Device Package 208-RQFP —
安裝類型 Surface Mount Surface Mount
工作溫度 [DATA_NEEDED: operating temperature range] —
Number of I/O Pins [DATA_NEEDED: user I/O count] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
MSL 等級 [DATA_NEEDED: moisture sensitivity level] —
Speed Grade -20 (20 ns) —
Device Family — MAX 9000 (EPM9320)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells — 320
Flip-Flops — 484
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5 V configurable
Package Lead Pitch — 0.500 mm
Number of Terminals — 208
工作溫度範圍 — -40C to +85C (Industrial)
In-System Programmability — Yes, 5.0 V ISP via JTAG
Configuration Memory — EEPROM (non-volatile)
Dedicated Input Pins — 4 (low-skew global distribution)
Minimum DC Input on I/O Pins — -0.5 V
Minimum DC Input on Dedicated Inputs — -0.3 V
Input Undershoot/ Overshoot — -2.0 V / 7.0 V for <20 ns (no-load)

資料表與資源

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