EPM9560ARC208-10 vs EPM9560ARC208-10N 比較
詳細並排比較 EPM9560ARC208-10 由 Intel 與 EPM9560ARC208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560ARC208-10 | EPM9560ARC208-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000A (Multiple Array MatriX) | — |
| Programmable Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macrocells | 560 macrocells | 560 |
| Logic Array Blocks | 35 LABs | — |
| User I/O Pins | 153 I/O | 153 |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Frequency | 144.9 MHz | — |
| 供應電壓 | 5.0 V | 5 V |
| Logic Family | CMOS | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP) | — |
| 工作溫度 | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad | 208-pin RQFP (PowerQuad II) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (N suffix) |
| 腳位數 | 208 pins | — |
| Family | — | MAX 9000 |
| Pin-to-Pin Delay | — | 10 ns |
| Internal Counter Frequency | — | 144.9 MHz |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG ISP) |
| Logic Array Blocks (LABs) | — | 20 |
| Speed Grade | — | -10 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |