EPM9560ARC208-10N vs EPM9560ARC240-10 比較
詳細並排比較 EPM9560ARC208-10N 由 Altera 與 EPM9560ARC240-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560ARC208-10N | EPM9560ARC240-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| 供應電壓 | 5 V | — |
| Technology | CMOS EEPROM | — |
| 封裝 | 208-pin RQFP (PowerQuad II) | 240-pin PowerQuad QFP (RQFP / EAR240) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability | Yes (JTAG ISP) | — |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | — |
| RoHS 狀態 | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| User I/Os (this package) | — | 191 (per Mouser listing) |
| Internal Frequency | — | 144.9 MHz |
| Propagation Delay (tpd) | — | 11.4 ns |
| Supply Voltage - Internal (VCCINT) | — | 5.0 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V (selectable) |
| Process Technology | — | CMOS EEPROM |
| Logic Family | — | CMOS |