EPM9560ARI208-10N vs EPM9560RI208-10N 比較
詳細並排比較 EPM9560ARI208-10N 由 Altera 與 EPM9560RI208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N Obsolete規格比較
| 參數 | EPM9560ARI208-10N | EPM9560RI208-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Maximum User I/O Pins | 212 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD1) | 10 ns | — |
| Clock-to-Output (tCO) | 4.5 ns | — |
| Setup Time (tSU) | 3.0 ns | — |
| Maximum Counter Frequency (fCNT) | 144.9 MHz | — |
| 供應電壓 | 5.0 V | 5 V |
| Logic Family | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable | — |
| 封裝 | 208-pin RQFP (Plastic) | 208-pin RQFP (PQFP) |
| 工作溫度 | 0 C to 70 C (Commercial) | -40C to +85C (Industrial grade, "RI" suffix) |
| 安裝類型 | Surface Mount | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| MSL 等級 | — | 3 (168 Hours) |
| RoHS 狀態 | — | ROHS3 Compliant (per fpgalink) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |