EPM9560GC280-15 vs EPM9560ARC240-10N 比較
詳細並排比較 EPM9560GC280-15 由 Altera 與 EPM9560ARC240-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteAltera
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N Obsolete規格比較
| 參數 | EPM9560GC280-15 | EPM9560ARC240-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | — |
| Macro Cells | 560 | 560 |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 安裝類型 | Through-Hole | Surface Mount |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | In-system, EEPROM-based (non-volatile) |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS 狀態 | Non-compliant (ceramic CPGA, contains lead) | Non-RoHS (legacy Altera part) |
| 生命週期狀態 | Obsolete (legacy Altera MAX 9000 family) | — |
| Logic Family | — | MAX 9000 (CPLD) |
| Process Technology | — | CMOS EEPROM |
| User I/Os | — | 191 |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency (fMAX) | — | 145 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| 工作溫度 | — | 0°C to +70°C (Commercial) |
| 封裝 | — | 240-pin RQFP (32x32 mm) |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| I/O Standard | — | 5.0 V TTL-compatible |