EPM9560GC280-15 vs EPM9560GM280-15 比較
詳細並排比較 EPM9560GC280-15 由 Altera 與 EPM9560GM280-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete規格比較
| 參數 | EPM9560GC280-15 | EPM9560GM280-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | EE PLD (EEPROM-based) |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 安裝類型 | Through-Hole | — |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS 狀態 | Non-compliant (ceramic CPGA, contains lead) | ROHS3 Compliant |
| 生命週期狀態 | Obsolete (legacy Altera MAX 9000 family) | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O | — | 216 |
| Logic Array Blocks (LABs) | — | 35 (16 macrocells each) |
| Supply Voltage (Nominal) | — | 5.0 V |
| Supply Voltage (Max) | — | 5.5 V |
| I/O Logic Level Support | — | 3.3 V or 5 V |
| Pin-to-Pin Delay (tPD) | — | 15 ns (speed grade -15) |
| 封裝 | — | FineLine BGA-280 (GM) |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5V ISP via JTAG IEEE 1149.1) |
| 工作溫度 | — | -40C to +85C (industrial) |
| MSL 等級 | — | 3 (168 Hours) |