EPM9560RC208-7 vs EPM9560RC208-10N 比較

詳細並排比較 EPM9560RC208-7 由 Altera 與 EPM9560RC208-10N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ 最後購買機會

規格比較

參數 EPM9560RC208-7 EPM9560RC208-10N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Family MAX 9000 MAX 9000
Device Type EPLD / CPLD —
Usable Gates 560 12,000
Macrocells 16 —
Logic Array Blocks (LABs) 4 16
User I/O Pins 208 153
Pin-to-Pin Delay (tPD) 7 ns (speed grade -7) —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Supply Voltage (VCCINT) 5.0 V 5.0 V
Supply Voltage (VCCIO) 5.0 V (TTL) or 3.3 V (LVCMOS with level translator) —
Process Technology 0.65 um CMOS EEPROM CMOS EEPROM
Configuration Memory Non-volatile on-chip EEPROM (no boot PROM required) —
Programming Interface JTAG (IEEE 1149.1) + Altera ISP —
封裝 208-pin Power Quad Flat Pack (RQFP-208) 208-pin RQFP (Power Quad Flat Pack)
工作溫度 0C to +70C (commercial) / -40C to +85C (industrial) [DATA_NEEDED: operating temperature grade]
Output Drive Current 160 mA DC sink per pin —
RoHS 狀態 Compliant (ROHS3 per distributor listing) [DATA_NEEDED: RoHS status]
Device — EPM9560
Macro Cells — 560
Pin-to-Pin Delay (tPD1) — 10 ns
I/O Bank Voltage (VCCIO) — 5.0 V
安裝類型 — Surface Mount
Programmability — In-system via IEEE 1149.1 JTAG

資料表與資源

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