EPM9560RI208-20N vs EPM9560RI208-15N 比較
詳細並排比較 EPM9560RI208-20N 由 Intel 與 EPM9560RI208-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RI208-20N | EPM9560RI208-15N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封裝 | 208-pin RQFP | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | Industrial (-40C to +85C) | 0C to 70C (Commercial) |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | — | CMOS EEPROM, in-system programmable |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |