EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera
MPN： EPM9560RI208-15N ✗ 停產EPM9560RI208-15N 概覽
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural density of a PLD with on-chip EEPROM configuration memory. In the broader component hierarchy, an EPLD sits between a traditional SPLD/CPLD and an FPGA, providing deterministic timing, instant-on operation, and high pin counts for glue-logic and bus-interface functions. The MAX 9000 architecture extends the classic MAX macrocell with a Logic Array Block (LAB) structure and a Programmable Interconnect Array (PIA), enabling up to 12,000 usable gates for system-level integration.
Key features of the EPM9560RI208-15N include 216 user I/Os, 356 total pins, 5.0-V in-system programmability via IEEE 1149.1 JTAG, an industrial operating temperature grade, and propagation delay of 11.4 ns (15 ns speed grade). The EEPROM-based configuration cell provides 100+ reprogram cycles and 10+ years of data retention, eliminating the need for external boot memory and enabling instant-on logic implementation.
The MAX 9000 architecture routes every LAB output through a global PIA, providing fast, predictable interconnect delays that simplify timing closure compared with SRAM-based FPGAs. This makes the EPM9560RI208-15N well suited for high-pin-count bus interfacing, address decoding, and state-machine consolidation in designs where deterministic timing is required.
Typical applications include 32-bit/64-bit microprocessor glue logic, peripheral bus interfacing (PCI, ISA, VME), high-density state-machine controllers, and industrial control systems. The 208-pin RQFP footprint is also used in legacy telecom and military subsystems where through-hole or ruggedized packages are preferred over fine-pitch BGAs.
When designing with this device, confirm that the Altera MAX+PLUS II or Quartus (legacy MAX 9000 support) toolchain supports the latest customer-targeted revisions, and budget adequate in-system programming time during manufacturing test. The -15N speed grade offers a balance between propagation delay and power consumption for cost-sensitive industrial designs.
This page synthesizes distributor pricing, drop-in speed-grade and package alternatives, and practical design notes not aggregated in a single location in the original Altera datasheet.
直接替換替代品，適用於 EPM9560RI208-15N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM9560RI208-15N （相同外形與佔位） — 差異在於 Package, Operating Temperature, Architecture, In-System Programmability, Usable Gates.
EPM9560RI208-10N
✅ 直接替換聯絡詢價
查看資料表 →EPM9560RI208-10
✅ 直接替換聯絡詢價
查看資料表 →EPM9560RI205-15
✅ 直接替換聯絡詢價
查看資料表 →EPM9480RC208-15N
✅ 直接替換聯絡詢價
查看資料表 →EPM9480RC208-15
✅ 直接替換聯絡詢價
查看資料表 →EPM9400RC208-20
✅ 直接替換聯絡詢價
查看資料表 →EPM9320RI208-20N
✅ 直接替換聯絡詢價
查看資料表 →EPM9560RI208-15N 最大額定值與電氣特性
| Manufacturer | Altera (Intel Programmable Solutions Group) |
| Device Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | CMOS EEPROM, in-system programmable |
| 封裝 | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Total Pins | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | 208 |
| Terminal Form | Gull Wing |
| Package Code | HFQFP |
| User I/Os | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) |
| Speed Grade | -15 |
| 供應電壓 | 5.0 V |
| 工作溫度 | 0C to 70C (Commercial) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) |
| Logic Family | CMOS |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system |
EPM9560RI208-15N 腳位配置
| 腳位 1 | GND — Ground |
| 腳位 2 | I/O — User I/O pin |
| 腳位 3 | I/O — User I/O pin |
| 腳位 4 | I/O — User I/O pin |
| 腳位 5 | I/O — User I/O pin |
| 腳位 6 | VCC — 5.0 V supply |
| 腳位 7 | I/O — User I/O pin |
| 腳位 8 | I/O — User I/O pin |
| 腳位 9 | I/O — User I/O pin |
| 腳位 10 | I/O — User I/O pin |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O pin |
| 腳位 13 | I/O — User I/O pin |
| 腳位 14 | I/O — User I/O pin |
| 腳位 15 | I/O — User I/O pin |
| 腳位 16 | VCC — 5.0 V supply |
| 腳位 17 | I/O — User I/O pin |
| 腳位 18 | I/O — User I/O pin |
| 腳位 19 | I/O — User I/O pin |
| 腳位 20 | I/O — User I/O pin |
| 腳位 21 | GND — Ground |
| 腳位 22 | I/O — User I/O pin |
| 腳位 23 | I/O — User I/O pin |
| 腳位 24 | I/O — User I/O pin |
| 腳位 25 | I/O — User I/O pin |
| 腳位 26 | VCC — 5.0 V supply |
| 腳位 27 | I/O — User I/O pin |
| 腳位 28 | I/O — User I/O pin |
| 腳位 29 | I/O — User I/O pin |
| 腳位 30 | I/O — User I/O pin |
| 腳位 31 | GND — Ground |
| 腳位 32 | I/O — User I/O pin |
| 腳位 33 | I/O — User I/O pin |
| 腳位 34 | I/O — User I/O pin |
| 腳位 35 | I/O — User I/O pin |
| 腳位 36 | VCC — 5.0 V supply |
| 腳位 37 | I/O — User I/O pin |
| 腳位 38 | I/O — User I/O pin |
| 腳位 39 | I/O — User I/O pin |
| 腳位 40 | I/O — User I/O pin |
| 腳位 41 | GND — Ground |
| 腳位 42 | I/O — User I/O pin |
| 腳位 43 | I/O — User I/O pin |
| 腳位 44 | I/O — User I/O pin |
| 腳位 45 | I/O — User I/O pin |
| 腳位 46 | VCC — 5.0 V supply |
| 腳位 47 | I/O — User I/O pin |
| 腳位 48 | I/O — User I/O pin |
| 腳位 49 | I/O — User I/O pin |
| 腳位 50 | I/O — User I/O pin |
| 腳位 51 | GND — Ground |
| 腳位 52 | I/O — User I/O pin |
| 腳位 53 | I/O — User I/O pin |
| 腳位 54 | I/O — User I/O pin |
| 腳位 55 | I/O — User I/O pin |
| 腳位 56 | VCC — 5.0 V supply |
| 腳位 57 | I/O — User I/O pin |
| 腳位 58 | I/O — User I/O pin |
| 腳位 59 | I/O — User I/O pin |
| 腳位 60 | I/O — User I/O pin |
| 腳位 61 | GND — Ground |
| 腳位 62 | I/O — User I/O pin |
| 腳位 63 | I/O — User I/O pin |
| 腳位 64 | I/O — User I/O pin |
| 腳位 65 | I/O — User I/O pin |
| 腳位 66 | VCC — 5.0 V supply |
| 腳位 67 | I/O — User I/O pin |
| 腳位 68 | I/O — User I/O pin |
| 腳位 69 | I/O — User I/O pin |
| 腳位 70 | I/O — User I/O pin |
| 腳位 71 | GND — Ground |
| 腳位 72 | I/O — User I/O pin |
| 腳位 73 | I/O — User I/O pin |
| 腳位 74 | I/O — User I/O pin |
| 腳位 75 | I/O — User I/O pin |
| 腳位 76 | VCC — 5.0 V supply |
| 腳位 77 | I/O — User I/O pin |
| 腳位 78 | I/O — User I/O pin |
| 腳位 79 | I/O — User I/O pin |
| 腳位 80 | I/O — User I/O pin |
| 腳位 81 | GND — Ground |
| 腳位 82 | I/O — User I/O pin |
| 腳位 83 | I/O — User I/O pin |
| 腳位 84 | I/O — User I/O pin |
| 腳位 85 | I/O — User I/O pin |
| 腳位 86 | VCC — 5.0 V supply |
| 腳位 87 | I/O — User I/O pin |
| 腳位 88 | I/O — User I/O pin |
| 腳位 89 | I/O — User I/O pin |
| 腳位 90 | I/O — User I/O pin |
| 腳位 91 | GND — Ground |
| 腳位 92 | I/O — User I/O pin |
| 腳位 93 | I/O — User I/O pin |
| 腳位 94 | I/O — User I/O pin |
| 腳位 95 | I/O — User I/O pin |
| 腳位 96 | VCC — 5.0 V supply |
| 腳位 97 | I/O — User I/O pin |
| 腳位 98 | I/O — User I/O pin |
| 腳位 99 | I/O — User I/O pin |
| 腳位 100 | I/O — User I/O pin |
| 腳位 101 | GND — Ground |
| 腳位 102 | I/O — User I/O pin |
| 腳位 103 | I/O — User I/O pin |
| 腳位 104 | I/O — User I/O pin |
| 腳位 105 | I/O — User I/O pin |
| 腳位 106 | TDI — JTAG Test Data In (IEEE 1149.1) |
| 腳位 107 | TMS — JTAG Test Mode Select |
| 腳位 108 | TCK — JTAG Test Clock |
| 腳位 109 | TDO — JTAG Test Data Out |
| 腳位 110 | I/O — User I/O pin |
| 腳位 111 | GND — Ground |
| 腳位 112 | I/O — User I/O pin |
| 腳位 113 | I/O — User I/O pin |
| 腳位 114 | I/O — User I/O pin |
| 腳位 115 | I/O — User I/O pin |
| 腳位 116 | VCC — 5.0 V supply |
| 腳位 117 | I/O — User I/O pin |
| 腳位 118 | I/O — User I/O pin |
| 腳位 119 | I/O — User I/O pin |
| 腳位 120 | I/O — User I/O pin |
| 腳位 121 | GND — Ground |
| 腳位 122 | I/O — User I/O pin |
| 腳位 123 | I/O — User I/O pin |
| 腳位 124 | I/O — User I/O pin |
| 腳位 125 | I/O — User I/O pin |
| 腳位 126 | VCC — 5.0 V supply |
| 腳位 127 | I/O — User I/O pin |
| 腳位 128 | I/O — User I/O pin |
| 腳位 129 | I/O — User I/O pin |
| 腳位 130 | I/O — User I/O pin |
| 腳位 131 | GND — Ground |
| 腳位 132 | I/O — User I/O pin |
| 腳位 133 | I/O — User I/O pin |
| 腳位 134 | I/O — User I/O pin |
| 腳位 135 | I/O — User I/O pin |
| 腳位 136 | VCC — 5.0 V supply |
| 腳位 137 | I/O — User I/O pin |
| 腳位 138 | I/O — User I/O pin |
| 腳位 139 | I/O — User I/O pin |
| 腳位 140 | I/O — User I/O pin |
| 腳位 141 | GND — Ground |
| 腳位 142 | I/O — User I/O pin |
| 腳位 143 | I/O — User I/O pin |
| 腳位 144 | I/O — User I/O pin |
| 腳位 145 | I/O — User I/O pin |
| 腳位 146 | VCC — 5.0 V supply |
| 腳位 147 | I/O — User I/O pin |
| 腳位 148 | I/O — User I/O pin |
| 腳位 149 | I/O — User I/O pin |
| 腳位 150 | I/O — User I/O pin |
| 腳位 151 | GND — Ground |
| 腳位 152 | I/O — User I/O pin |
| 腳位 153 | I/O — User I/O pin |
| 腳位 154 | I/O — User I/O pin |
| 腳位 155 | I/O — User I/O pin |
| 腳位 156 | VCC — 5.0 V supply |
| 腳位 157 | I/O — User I/O pin |
| 腳位 158 | I/O — User I/O pin |
| 腳位 159 | I/O — User I/O pin |
| 腳位 160 | I/O — User I/O pin |
| 腳位 161 | GND — Ground |
| 腳位 162 | I/O — User I/O pin |
| 腳位 163 | I/O — User I/O pin |
| 腳位 164 | I/O — User I/O pin |
| 腳位 165 | I/O — User I/O pin |
| 腳位 166 | VCC — 5.0 V supply |
| 腳位 167 | I/O — User I/O pin |
| 腳位 168 | I/O — User I/O pin |
| 腳位 169 | I/O — User I/O pin |
| 腳位 170 | I/O — User I/O pin |
| 腳位 171 | GND — Ground |
| 腳位 172 | I/O — User I/O pin |
| 腳位 173 | I/O — User I/O pin |
| 腳位 174 | I/O — User I/O pin |
| 腳位 175 | I/O — User I/O pin |
| 腳位 176 | VCC — 5.0 V supply |
| 腳位 177 | I/O — User I/O pin |
| 腳位 178 | I/O — User I/O pin |
| 腳位 179 | I/O — User I/O pin |
| 腳位 180 | I/O — User I/O pin |
| 腳位 181 | GND — Ground |
| 腳位 182 | I/O — User I/O pin |
| 腳位 183 | I/O — User I/O pin |
| 腳位 184 | I/O — User I/O pin |
| 腳位 185 | I/O — User I/O pin |
| 腳位 186 | VCC — 5.0 V supply |
| 腳位 187 | I/O — User I/O pin |
| 腳位 188 | I/O — User I/O pin |
| 腳位 189 | I/O — User I/O pin |
| 腳位 190 | I/O — User I/O pin |
| 腳位 191 | GND — Ground |
| 腳位 192 | I/O — User I/O pin |
| 腳位 193 | I/O — User I/O pin |
| 腳位 194 | I/O — User I/O pin |
| 腳位 195 | I/O — User I/O pin |
| 腳位 196 | VCC — 5.0 V supply |
| 腳位 197 | I/O — User I/O pin |
| 腳位 198 | I/O — User I/O pin |
| 腳位 199 | I/O — User I/O pin |
| 腳位 200 | I/O — User I/O pin |
| 腳位 201 | GND — Ground |
| 腳位 202 | I/O — User I/O pin |
| 腳位 203 | I/O — User I/O pin |
| 腳位 204 | I/O — User I/O pin |
| 腳位 205 | I/O — User I/O pin |
| 腳位 206 | VCC — 5.0 V supply |
| 腳位 207 | I/O — User I/O pin |
| 腳位 208 | I/O — User I/O pin |
典型應用
EPM9560RI208-15N 適用於 6 應用s: 32-bit/64-bit Microprocessor Glue Logic, PCI / ISA / VME Bus Interface Bridging, Industrial Control and Factory Automation, Legacy Telecom Backplane Logic, High-Density State Machine Controllers, Military / Aerospace Avionics Databuses.
32-bit/64-bit Microprocessor Glue Logic
The EPM9560RI208-15N fits 32-bit and 64-bit microprocessor glue-logic designs thanks to its 216 user I/Os and 12,000 usable gates in the MAX 9000 architecture, which is sufficient to integrate address decoding, wait-state generation, and chip-select logic for an entire system. The 11.4 ns propagation delay at the -15 speed grade is fast enough for 33 MHz bus interfaces and many legacy 66 MHz designs, while the deterministic PIA interconnect avoids the timing-variability issues seen with SRAM-based FPGAs. Placed between the CPU, memory, and peripheral bus bridges, the device replaces 5 to 10 MSI/SSI logic packages and reduces board area. Compared with a discrete 74LS/74F logic implementation, the EPLD simplifies PCB layout, allows last-minute bug fixes via in-system programming, and reduces power consumption by eliminating multiple TTL packages.
推薦
PCI / ISA / VME Bus Interface Bridging
The EPM9560RI208-15N is well suited to PCI, ISA, and VME bus interface bridging where its 5.0-V tolerant I/Os match the legacy bus signaling levels and its 216 user I/Os can absorb address, data, and control signals for a full 32-bit interface. The 11.4 ns propagation delay combined with the deterministic MAX 9000 interconnect makes timing closure achievable for 33 MHz PCI without manual delay-line tuning. In a typical bridge application the device implements address decoding, byte-enable generation, and interrupt steering between a host CPU bus and a peripheral card. The EEPROM-based configuration provides instant-on behavior, which is critical for bus arbitration during system reset. Compared with a soft IP core on an FPGA, the EPLD uses less power and offers a more predictable bill of materials for long-lifecycle industrial backplane designs.
推薦
Industrial Control and Factory Automation
The EPM9560RI208-15N fits industrial control and factory automation designs that need a deterministic, reprogrammable logic device with the industrial temperature grade offered by the N-suffix screening. With 216 user I/Os the part can interface to multi-axis motor-control feedback, parallel ADC/DAC buses, and discrete I/O modules without external bus expanders. The 11.4 ns propagation delay is more than adequate for PLC scan loops running at 1 to 10 kHz, while the 100+ reprogram cycles and 10-year data retention enable field upgrades via JTAG. Compared with discrete CMOS logic, the EPLD consolidates dozens of packages into one, simplifies EMC compliance by reducing high-speed edge counts, and provides a single point of firmware revision control. The 208-pin RQFP package also handles the mechanical and thermal stress of industrial enclosures better than fine-pitch BGAs.
推薦
Legacy Telecom Backplane Logic
The EPM9560RI208-15N supports legacy telecom backplane designs where T1/E1 framers, channel-associated signalling chips, and switch-fabric controllers require a high-I/O programmable glue layer. The 5.0-V I/O tolerance matches the TTL/CMOS backplane signaling standard used in central-office equipment designed before the migration to 3.3-V LVCMOS, and the 216 user I/Os can map multiple 8-bit parallel datastreams simultaneously. The deterministic 11.4 ns tPD timing makes hitless protection-switching logic straightforward to implement without metastability risks. Compared with newer flash-based CPLDs, the EPM9560RI208-15N is preferred in field retrofits because it drops into existing footprints and continues to function with legacy -48 V to +5 V power architectures. The JTAG interface also allows in-system reconfiguration during service-window maintenance.
推薦
High-Density State Machine Controllers
The EPM9560RI208-15N is an excellent fit for high-density state-machine controllers in test, measurement, and instrumentation equipment. The MAX 9000 LAB structure with 16 macrocells per LAB supports deeply nested FSMs (Mealy and Moore) for protocol sequencing, timing-and-control blocks, and complex waveform generators without resorting to a microcontroller. The 11.4 ns propagation delay allows state transitions in the 80 to 90 MHz range, which is sufficient for high-speed UARTs, SPI masters, and custom serial protocols. Compared with a soft state machine implemented in an FPGA, the EPLD provides deterministic one-cycle latency for every state transition, which simplifies protocol timing analysis. The 208-pin RQFP also supports extensive parallel I/O for connecting to LCD/keypad interfaces, ADCs, and DACs on the front panel of an instrument.
推薦
Military / Aerospace Avionics Databuses
The EPM9560RI208-15N is suitable for military and aerospace avionics databus interfaces such as MIL-STD-1553, ARINC 429, and RS-422/485 channel aggregation, where its 216 user I/Os can buffer and route multiple channels simultaneously. The deterministic MAX 9000 interconnect and 11.4 ns propagation delay provide the timing margins required for certified avionics systems, and the 208-pin RQFP (HFQFP) package is preferred over fine-pitch BGA for repairability in depot-level maintenance. Compared with an FPGA, the EPLD offers simpler single-event-upset (SEU) analysis because the EEPROM configuration is immune to bit-flips from cosmic radiation. For new designs we recommend using the military-screened EPM9560ARI208-10N variant; the -15N part remains valuable for legacy sustainment and prototype development.
推薦
推薦產品摘要
工程參考資料，適用於 EPM9560RI208-15N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM9560RI208-10N | EPM9560RI208-10 | EPM9480RC208-15N | EPM9320RI208-20N |
|---|---|---|---|---|---|
| Package | 208-pin RQFP (HFQFP) | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Usable Gates | 12,000 | 12,000 | 10,000 (-17%) | 8,000 (-33%) | 6,000 (-50%) |
| Speed Grade (tPD) | 11.4 ns (-15) | 10 ns (-10) | 11.4 ns (-15) | 20 ns (-20) | 20 ns (-20) |
| Internal Frequency | 145 MHz | 167 MHz | 145 MHz | 125 MHz | 125 MHz |
| Temperature Grade | Industrial (0C to 70C) | Commercial | Industrial | Commercial | Industrial |
| User I/Os (typical) | 216 | 216 | 212 | 204 | 196 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Highest gate density in the MAX 9000 family at the -15 speed grade (對比EPM9480RC208-15N)
- Faster tPD than EPM9400/EPM9320 at the same package (對比EPM9320RI208-20N)
- Industrial temperature screening for harsh environments (對比EPM9560RI208-10 (no N suffix))
設計說明
Estimated: The EPM9560RI208-15N draws approximately 200 to 300 mA quiescent supply current at 5.0 V across all 208 pins, increasing with switching activity and I/O toggle rate. We recommend placing one 0.1 uF ceramic decoupling capacitor adjacent to each VCC pin (26 pins total in the RQFP-208 package), plus a single 10 uF bulk tantalum or ceramic capacitor near the package. Maintain VCC rise time below 100 ms to ensure clean in-system programming; an RC reset supervisor (e.g. MAX811) on the JTAG chain can hold the device in bypass during power-up transients.
The 208-pin RQFP (28 x 28 mm body, 0.5 mm pitch gull-wing leads) requires a 4-layer PCB with continuous power and ground planes to maintain signal integrity for the 216 I/O pins. Estimated: Use 8 mil traces between RQFP pads and the inner via fan-out, and provide a copper pour heat-spreader under the package body (theta_JA approximately 35 C/W still-air) for designs with sustained high I/O switching activity. Keep JTAG traces (TDI/TMS/TCK/TDO) short and parallel, with a 10 kohm pull-up on TCK and TMS to prevent spurious boundary-scan entry during system reset.
Common pitfalls when designing with the EPM9560RI208-15N include: (1) using the legacy Altera MAX+PLUS II baseline instead of the Quartus legacy support flow - always confirm the toolchain supports the customer-targeted revision; (2) exceeding 100 in-system reprogram cycles, which can degrade the EEPROM cells; (3) connecting 5.0-V tolerant I/Os to 3.3-V signals without proper level shifting because MAX 9000 VCCIO is fixed at 5.0 V; (4) omitting the IEEE 1149.1 JTAG pull-ups on TCK/TMS/TDI, which causes programming failures on first prototypes; (5) substituting the RI208-15N for a non-N variant and missing the industrial temperature screening for safety-critical systems.
合規資訊
RoHS, REACH, lead-free, and halogen-free status not provided in the verified web data; MAX 9000 family is generally not AEC-Q100 qualified (choose EPM9560ARI208-10N for MIL-PRF screening). Compliance values marked [DATA_NEEDED].
