K3K9K90BM-MGCP vs K3LKBKB0BM-MGCP 比較
詳細並排比較 K3K9K90BM-MGCP 由 Samsung Electronics 與 K3LKBKB0BM-MGCP 由 Samsung Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | K3K9K90BM-MGCP | K3LKBKB0BM-MGCP |
|---|---|---|
| 品牌 | Samsung Electronics | Samsung Electronics |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 單價 (USD) | — | $46.62 |
| 記憶體類型 | LPDDR5 SDRAM (CMOS) | DRAM (LPDDR5 SDRAM) |
| 組織 | [DATA_NEEDED: density and organization] | 1G x 32 |
| Pin Speed | Up to 6400 Mbps (family maximum per Samsung LPDDR5 page) | — |
| Interface Width | x32 (family standard for K3K/K3L BM packages) | — |
| 封裝 | PBGA (Plastic Ball Grid Array) | FBGA-315 |
| Ball Count | [DATA_NEEDED: ball count] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -25C to +85C |
| Supply Voltage (VDD) | [DATA_NEEDED: VDD voltage] | — |
| Refresh | Self-refresh with per-bank refresh support (LPDDR5 standard) | Self-refresh and auto-refresh (LPDDR5 standard) |
| Power Saving vs LPDDR4X | Approximately 20% (Samsung published figure) | — |
| Max Bandwidth | Up to 51.2 GB/s (family maximum per Samsung LPDDR5 page) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Clocking | WCK (word clock) architecture | — |
| Standards | JEDEC LPDDR5 | — |
| 記憶體容量 | — | 32 Gbit |
| 資料速率 | — | 6400 Mbps per pin |
| Supply Voltage Rails | — | 500 mV, 900 mV, 1.05 V, 1.8 V |
| 介面 | — | LPDDR5 x32 |
| Technology Generation | — | LPDDR5 (JEDEC LPDDR5 family) |
| Density per Package | — | 4 GB (32 Gbit) |
| Application Segment | — | Mobile, embedded, industrial computing |
| Standby / Deep Sleep | — | LPDDR5 deep-sleep power states |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| Access Time / Latency | — | [DATA_NEEDED: CAS latency] |