K3LKBKB0BM-MGCP vs K3K9K90BM-MGCP 比較
詳細並排比較 K3LKBKB0BM-MGCP 由 Samsung Electronics 與 K3K9K90BM-MGCP 由 Samsung Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | K3LKBKB0BM-MGCP | K3K9K90BM-MGCP |
|---|---|---|
| 品牌 | Samsung Electronics | Samsung Electronics |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 單價 (USD) | $46.62 | — |
| 記憶體類型 | DRAM (LPDDR5 SDRAM) | LPDDR5 SDRAM (CMOS) |
| 記憶體容量 | 32 Gbit | — |
| 組織 | 1G x 32 | [DATA_NEEDED: density and organization] |
| 資料速率 | 6400 Mbps per pin | — |
| Supply Voltage Rails | 500 mV, 900 mV, 1.05 V, 1.8 V | — |
| 介面 | LPDDR5 x32 | — |
| 封裝 | FBGA-315 | PBGA (Plastic Ball Grid Array) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -25C to +85C | [DATA_NEEDED: operating temperature range] |
| Technology Generation | LPDDR5 (JEDEC LPDDR5 family) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Density per Package | 4 GB (32 Gbit) | — |
| Refresh | Self-refresh and auto-refresh (LPDDR5 standard) | Self-refresh with per-bank refresh support (LPDDR5 standard) |
| Application Segment | Mobile, embedded, industrial computing | — |
| Standby / Deep Sleep | LPDDR5 deep-sleep power states | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Access Time / Latency | [DATA_NEEDED: CAS latency] | — |
| Pin Speed | — | Up to 6400 Mbps (family maximum per Samsung LPDDR5 page) |
| Interface Width | — | x32 (family standard for K3K/K3L BM packages) |
| Ball Count | — | [DATA_NEEDED: ball count] |
| Supply Voltage (VDD) | — | [DATA_NEEDED: VDD voltage] |
| Power Saving vs LPDDR4X | — | Approximately 20% (Samsung published figure) |
| Max Bandwidth | — | Up to 51.2 GB/s (family maximum per Samsung LPDDR5 page) |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |
| Clocking | — | WCK (word clock) architecture |
| Standards | — | JEDEC LPDDR5 |