SN65LVDS105PWR vs SN65LVDS105PWRG4 比較
詳細並排比較 SN65LVDS105PWR 由 Texas Instruments 與 SN65LVDS105PWRG4 由 Texas Instruments. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Texas Instruments
SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWRG4 ✗ 停產規格比較
| 參數 | SN65LVDS105PWR | SN65LVDS105PWRG4 |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 類別 | Clock & Timing | Clock & Timing |
| 生命週期狀態 | 啟用中 | 停產終止 |
| 功能 | 1 LVTTL input to 4 LVDS output repeater / fanout buffer | 1 LVTTL to 4 LVDS clock fanout buffer / repeater |
| 資料速率 | 400 Mbps | — |
| Max Clock Frequency | 400 MHz | — |
| 供應電壓 | 3 V to 3.6 V (typical 3.3 V) | — |
| Input Type | LVTTL (single-ended) | LVTTL |
| 輸出類型 | LVDS (differential), 4 pairs | LVDS (4 differential pairs) |
| Output Voltage (typical) | 350 mV into 100 ohm load | — |
| Standard Compliance | ANSI EIA/TIA-644 LVDS | — |
| 通道數 | 1 x 1:4 | — |
| 封裝 | 16-TSSOP (PW) | TSSOP-16 (PW), 5 mm x 6.4 mm |
| 安裝類型 | Surface Mount | Surface Mount |
| Technology | LVDS differential signaling | — |
| 類別 | Signal Buffers, Repeaters, Splitters - Clock Buffer | Interface - Signal Buffers, Repeaters, Splitters |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| 靜態電流 | [DATA_NEEDED: quiescent current] | — |
| Input Rise/Fall Time Note | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance | — |
| Configuration | — | 1 x 1:4 Channel |
| Max Data Rate | — | 400 Mbps |
| Supply Voltage Range | — | 3 V to 3.6 V |
| Typical Propagation Delay | — | 2.2 ns |
| Typical LVDS Output Voltage | — | 285 mV into 100 ohm load |
| Signaling Standard | — | ANSI EIA/TIA-644 (LVDS) |
| Bus-Terminal ESD Rating | — | Exceeds 12 kV |
| Packaging | — | Tape & Reel (PWR suffix) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| 生命週期狀態 | — | Discontinued at Digi-Key |