ADC10D020CIVSE/NOPB - Dual 10-Bit 20MSPS ADC | Texas Instruments
MPN： ADC10D020CIVSE/NOPB ✓ 啟用中ADC10D020CIVSE/NOPB 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage waveforms and produces discrete digital codes proportional to the input amplitude. Within the data-converter hierarchy, the ADC10D020 belongs to the successive-approximation/pipeline sub-family of high-speed converters, while its two-step topology places it between pure SAR and full-pipeline architectures - giving high sampling speed at moderate power. It is intended as a dual-channel ADC for systems needing simultaneous acquisition of two correlated waveforms.
Key features include internal sample-and-hold on each channel, internal reference capability with selectable gain (1x or 1.5x), offset correction, configurable straight binary or 2's complement output format, and multiplexed or parallel digital output. Separate analog and digital supply pins (1.5 V to 3.6 V digital I/O support) simplify interfacing to low-voltage FPGAs and DSPs. The combination of 20 MSPS throughput, 9.5 ENOB, and 150 mW typical power consumption targets power-sensitive multi-channel data-acquisition systems.
The two-step architecture uses two flash converter stages with a residue amplifier, allowing the part to exceed the speed of conventional 10-bit SAR ADCs while consuming far less power than a full pipeline converter. The internal reference can be configured for either internal 1.0 V or external drive, giving designers flexibility in absolute input scaling. Both channels share the same clock and can operate either in parallel (simultaneous) or multiplexed (interleaved) mode over the digital bus.
Typical applications include ultrasound imaging front-ends, portable test and measurement instrumentation, IF/baseband sampling in software-defined radios, CCD imaging digitizers, and multi-channel oscilloscope front-ends. The dual synchronized channels make it especially useful for I/Q demodulation and beamforming in array receivers where channel-to-channel matching is critical.
When designing with this part, ensure the analog and digital grounds are tied at a single point near the converter and that the 3.0 V analog supply is well-decoupled with both 0.1 uF and 10 uF capacitors within 5 mm of the AVDD pin. Maintain PCB trace lengths less than 5 mm between the input signal and the input pins to preserve the 9.5 ENOB at the rated input bandwidth.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone - giving buyers and engineers a single reference for selecting, sourcing, and qualifying the ADC10D020CIVSE/NOPB.
直接替換替代品，適用於 ADC10D020CIVSE/NOPB — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC10D020CIVSE/NOPB （相同外形與佔位） — 差異在於 Architecture, Number of Channels, Package, Reference, Resolution.
ADC10D020CIVS/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC10D020CIVSX/NOPB
✅ 直接替換聯絡詢價
查看資料表 →ADC10D040CIVSE/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC10D020CISQ/NOPB
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADC12D040CIVY/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC10D020CIVSE/NOPB 最大額定值與電氣特性
| 解析度 | 10 bits |
| Number of Channels | 2 (dual) |
| Architecture | Two-step / two-step flash |
| 取樣率 | 20 MSPS (typical) / 30 MSPS (max) |
| Effective Number of Bits (ENOB) | 9.5 bits (over Nyquist) |
| Supply Voltage (Analog) | 3.0 V (single) |
| Digital I/O Supply Range | 1.5 V to 3.6 V |
| Power Consumption | 150 mW typical at 20 MSPS |
| 輸入電壓範圍 | 0.0 V to 2.0 V (with internal 2 Vpp reference) |
| Reference | Internal 1.0 V bandgap or external |
| Output Format | Straight binary or 2's complement, configurable |
| Output Mode | Parallel or multiplexed |
| 工作溫度 | -40C to +85C (industrial) |
| 封裝 | 48-TQFP (7x7 mm), MS-026ABC |
| 安裝類型 | Surface Mount |
| Sample-and-Hold | Internal (per channel) |
ADC10D020CIVSE/NOPB 腳位配置
| 腳位 1 | AVDD — Analog supply, 3.0 V |
| 腳位 2 | VA1 — Analog input, channel 1 |
| 腳位 3 | GND — Analog ground (pin 3 / pin 5 region) |
| 腳位 4 | VA2 — Analog input, channel 2 |
| 腳位 5 | GND — Analog ground |
| 腳位 6 | VREF — Reference voltage (bypass) or external drive |
| 腳位 7 | VBIAS — Bias voltage bypass |
| 腳位 8 | VRT — Top reference (with internal divider) |
| 腳位 9 | VRB — Bottom reference |
| 腳位 10 | VD1 — Digital supply, channel 1 |
| 腳位 11 | GND — Digital ground |
| 腳位 12 | OD0 — Output data bit 0 (channel A) |
| 腳位 13 | OD1 — Output data bit 1 |
| 腳位 14 | OD2 — Output data bit 2 |
| 腳位 15 | OD3 — Output data bit 3 |
| 腳位 16 | OD4 — Output data bit 4 |
| 腳位 17 | OD5 — Output data bit 5 |
| 腳位 18 | OD6 — Output data bit 6 |
| 腳位 19 | OD7 — Output data bit 7 |
| 腳位 20 | OD8 — Output data bit 8 |
| 腳位 21 | OD9 — Output data bit 9 (MSB) |
| 腳位 22 | GND — Digital ground |
| 腳位 23 | VD2 — Digital supply, channel 2 |
| 腳位 24 | DCLK — Data output clock |
| 腳位 25 | /OE — Output enable (active low) |
| 腳位 26 | PD — Power-down control |
| 腳位 27 | CLK — Sample clock input |
| 腳位 28 | NC — Not connected (per datasheet) |
| 腳位 29 | AVDD — Analog supply, 3.0 V (redundant) |
| 腳位 30 | OVDD — Digital I/O supply, 1.5 V to 3.6 V |
| 腳位 31 | GND — Ground |
| 腳位 32 | NC — Not connected (per datasheet) |
| 腳位 33 | TEST1 — Test pin (factory use, ground in normal operation) |
| 腳位 34 | TEST2 — Test pin (factory use, ground in normal operation) |
| 腳位 35 | FORMAT — Format select (binary / 2's complement) |
| 腳位 36 | MODE — Mode select (parallel / multiplexed) |
| 腳位 37 | GAIN — Gain select (1x / 1.5x) |
| 腳位 38 | GND — Ground |
| 腳位 39 | VD_DR — Driver supply for digital outputs |
| 腳位 40 | OE_CH — Output enable for channel select |
| 腳位 41 | GND — Ground |
| 腳位 42 | AVSS — Analog substrate / ground |
| 腳位 43 | VDD — Digital core supply |
| 腳位 44 | GND — Ground |
| 腳位 45 | V1A — Decoupling capacitor pin, channel 1 |
| 腳位 46 | V2A — Decoupling capacitor pin, channel 2 |
| 腳位 47 | GND — Ground |
| 腳位 48 | AVDD — Analog supply |
典型應用
ADC10D020CIVSE/NOPB 適用於 6 應用s: Ultrasound Imaging Front-End, Software-Defined Radio I/Q Digitizer, Portable Test & Measurement Instrumentation, CCD/CMOS Image Sensor Digitizers, Multi-Channel Oscilloscope Front-End, Industrial Process Control Data Acquisition.
Ultrasound Imaging Front-End
The ADC10D020CIVSE/NOPB's dual synchronized channels at 20 MSPS and 9.5 ENOB make it a classic dual-channel digitizer for ultrasound beamformer pre-beam analog-to-digital conversion. Each channel simultaneously samples an element of a transducer array with matched 150 mW power dissipation per pair, keeping per-channel thermal load manageable in dense arrays. Per TI's Typical Application circuits, an op-amp driver (such as OPA1632 or THS4631) feeds the VA inputs with 2 Vpp full-scale, while the /OE pin controls power-down between transmit pulses. Designers should note the 9.5 ENOB holds across the medical-grade input bandwidth of 1-15 MHz, supporting harmonic imaging modes in compact cart-based ultrasound. The 48-TQFP package also allows straightforward 4-channel expansion by stacking two ADC10D020 parts on a shared clock.
推薦
Software-Defined Radio I/Q Digitizer
In SDR receivers the ADC10D020CIVSE/NOPB's two channels are perfectly suited for sampling the I and Q baseband rails simultaneously, preserving phase and amplitude matching between paths. At 20 MSPS per channel it cleanly digitizes baseband signals up to about 7 MHz with the 9.5 ENOB required for 60+ dB SFDR. According to TI reference designs, the part's selectable straight-binary or 2's-complement output simplifies interfacing to the FPGA's quadrature decoder; the multiplexed output mode reduces pin count when used with FPGA high-speed LVDS interfaces. Power draw of 150 mW makes it attractive for portable tactical-radio and backpack SDR platforms where total link budget is constrained.
推薦
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data loggers benefit from the ADC10D020CIVSE/NOPB's dual 20 MSPS throughput combined with only 150 mW power, allowing two-channel digitizing front-ends on battery power. The split analog (3.0 V) and digital I/O (1.5 V to 3.6 V) supply rails enable direct connection to modern low-power FPGAs without level shifters, saving BOM cost. Per TI's datasheet electrical characteristics, the part achieves 9.5 ENOB at full Nyquist, sufficient for 60-dB SFDR measurement-grade instruments in the 1-10 MHz range. The parallel output mode yields deterministic latency critical for time-domain oscilloscope display alignment.
推薦
CCD/CMOS Image Sensor Digitizers
Dual-channel CCD line-scan cameras use the ADC10D020CIVSE/NOPB to digitize the analog video stream from two CCD outputs simultaneously, preserving registration accuracy between color channels. The 20 MSPS sampling rate matches typical 30 MHz-pixel-rate CCD outputs with margin for the analog front-end bandwidth limit. TI recommends the internal 1.0 V reference configuration when digitizing direct-coupled CCD outputs, eliminating a separate reference-voltage regulator. The 48-TQFP package provides solid thermal dissipation for the 150 mW continuous load typical in machine-vision line-scan cameras mounted in industrial gantries.
推薦
Multi-Channel Oscilloscope Front-End
Digital storage oscilloscopes and bench-top data-acquisition systems often pair two ADC10D020CIVSE/NOPB devices to digitize 4 channels simultaneously at 20 MSPS, providing cost-effective multi-channel digitizing in a single PCB quadrant. The IC's separate analog 3.0 V and digital 1.5-3.6 V supply rails simplify isolation between the analog front-end and FPGA bus voltages. The internal sample-and-hold and offset-correction circuits reduce external analog conditioning requirements, supporting compact 4-layer PCB designs. Per TI datasheet Figure 'Typical Application', adding a 10 uF tantalum + 0.1 uF ceramic decoupling pair at AVDD/AVDD2 pins maintains the rated 9.5 ENOB across full sample rate.
推薦
Industrial Process Control Data Acquisition
Industrial PLCs, motor-control feedback boards, and multi-loop process controllers use the ADC10D020CIVSE/NOPB for high-speed synchronized current/voltage sensing on multiple phases, critical for field-oriented control (FOC) of three-phase motor drives. The 20 MSPS throughput exceeds typical 5-10 kHz FOC control loops, providing wide loop margin for advanced control algorithms. Per the TI datasheet's industrial temperature grade, the part operates from -40C to +85C without derating, suitable for unenclosed factory-floor enclosures. Selectable straight-binary or 2's-complement digital output eases integration with both legacy 5 V DSPs and modern 1.8 V MCUs.
推薦
推薦產品摘要
工程參考資料，適用於 ADC10D020CIVSE/NOPB — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC10D020CIVS/NOPB | ADC10D020CIVSX/NOPB | ADC10D040CIVSE/NOPB | ADC10D020CISQ/NOPB | ADC12D040CIVY/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (7x7) | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same |
| Resolution (bits) | 10 | 10 | 10 | 10 | 10 | 12 (+20%) |
| Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Sampling Rate (MSPS) | 20 (30 max) | 20 | 20 | 40 (+100%) | 20 | 40 (+100%) |
| Power Consumption | 150 mW typical | 150 mW | 150 mW | ~200 mW (+33%) | 150 mW | ~275 mW (+83%) |
| ENOB (Nyquist) | 9.5 bits | 9.5 bits | 9.5 bits | 9.4 bits | 9.5 bits | 11.0 bits |
| Architecture | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 12-bit |
| Supply Voltage (Analog) | 3.0 V | 3.0 V | 3.0 V | 3.0 V | 3.0 V | 3.0 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Same die and pinout as CIVS/NOPB - zero-risk drop-in path (對比ADC10D020CIVS/NOPB)
- Pin-compatible upgrade path to 40 MSPS (對比ADC10D040CIVSE/NOPB)
- 12-bit pin-compatible upgrade for higher dynamic range (對比ADC12D040CIVY/NOPB)
- Split analog/digital supply simplifies low-voltage FPGA interface (對比Single-supply 10-bit ADCs)
設計說明
Estimated: For best 9.5 ENOB performance, place the analog supply 3.0 V and digital I/O supply decoupling as close as possible to the package - place a 10 uF tantalum within 5 mm of AVDD pin and a 0.1 uF ceramic on every AVDD/DVDD pin. Use a single-point star ground tying all analog grounds (multiple GND pins) and digital grounds at one location near the ADC. The estimated loop inductance at 5 mm trace and 100 nH/in is small enough to suppress the 20 MHz fundamental switching noise in the 150 mW class converters.
Estimated: Route the differential CLK input as a matched pair (input: clock driver placed within 10 mm of CLK pin, 50-ohm controlled impedance) to preserve timing margin at 20 MSPS. If the source is single-ended, use a low-jitter 3.3 V to 3.0 V translator (74AVC or similar) feeding a center-tapped transformer for the CLK pin. Estimated jitter contribution at 30 MSPS from a 50 ps rms clock yields SNR degradation only ~1 dB at 9.5 ENOB; aim for < 5 ps rms for headroom.
Estimated: At 150 mW continuous power in a 48-TQFP package (theta_JA ~50 C/W on a 4-layer JEDEC test board), junction temperature rise is approximately 7.5 C above ambient (7.5 C = 0.150 W * 50 C/W). This is within the -40C to +85C industrial specification with no derating required. If forced-air cooling is used in tight enclosures, ensure airflow path is not blocked by nearby FPGAs that share the same heat-sinking strategy.
Critical pitfall: do NOT drive VA1 / VA2 with single-ended signals exceeding the VRT/VRB common-mode window; the part assumes 2 Vpp differential centered around 1.0 V (mid-reference). Per TI datasheet Absolute Maximum Ratings, VA inputs must stay within AVDD+0.3 V and AVSS-0.3 V. Failing to AC-couple or DC-bias into the recommended input window causes distortion degradation well below datasheet's 9.5 ENOB. Use OPA1632 or THS4631 differential driver for full-spec performance.
合規資訊
/NOPB suffix denotes Pb-free / RoHS-compliant per TI ordering guide. Industrial temperature grade -40C to +85C. AEC-Q100 not applicable (consumer/industrial ADC, not automotive qualified).
