ADC10D020CIVSE/NOPB - Dual 10-Bit 20MSPS ADC | Texas Instruments
MPN: ADC10D020CIVSE/NOPB ✓ Hoạt độngADC10D020CIVSE/NOPB Tóm tắt
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage waveforms and produces discrete digital codes proportional to the input amplitude. Within the data-converter hierarchy, the ADC10D020 belongs to the successive-approximation/pipeline sub-family of high-speed converters, while its two-step topology places it between pure SAR and full-pipeline architectures - giving high sampling speed at moderate power. It is intended as a dual-channel ADC for systems needing simultaneous acquisition of two correlated waveforms.
Key features include internal sample-and-hold on each channel, internal reference capability with selectable gain (1x or 1.5x), offset correction, configurable straight binary or 2's complement output format, and multiplexed or parallel digital output. Separate analog and digital supply pins (1.5 V to 3.6 V digital I/O support) simplify interfacing to low-voltage FPGAs and DSPs. The combination of 20 MSPS throughput, 9.5 ENOB, and 150 mW typical power consumption targets power-sensitive multi-channel data-acquisition systems.
The two-step architecture uses two flash converter stages with a residue amplifier, allowing the part to exceed the speed of conventional 10-bit SAR ADCs while consuming far less power than a full pipeline converter. The internal reference can be configured for either internal 1.0 V or external drive, giving designers flexibility in absolute input scaling. Both channels share the same clock and can operate either in parallel (simultaneous) or multiplexed (interleaved) mode over the digital bus.
Typical applications include ultrasound imaging front-ends, portable test and measurement instrumentation, IF/baseband sampling in software-defined radios, CCD imaging digitizers, and multi-channel oscilloscope front-ends. The dual synchronized channels make it especially useful for I/Q demodulation and beamforming in array receivers where channel-to-channel matching is critical.
When designing with this part, ensure the analog and digital grounds are tied at a single point near the converter and that the 3.0 V analog supply is well-decoupled with both 0.1 uF and 10 uF capacitors within 5 mm of the AVDD pin. Maintain PCB trace lengths less than 5 mm between the input signal and the input pins to preserve the 9.5 ENOB at the rated input bandwidth.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone - giving buyers and engineers a single reference for selecting, sourcing, and qualifying the ADC10D020CIVSE/NOPB.
Bộ thay thế dễ dàng lắp đặt cho ADC10D020CIVSE/NOPB — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADC10D020CIVSE/NOPB (cùng hình factor và footprint) — khác nhau ở Architecture, Number of Channels, Package, Reference, Resolution.
ADC10D020CIVS/NOPB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC10D020CIVSX/NOPB
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC10D040CIVSE/NOPB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC10D020CISQ/NOPB
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
ADC12D040CIVY/NOPB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC10D020CIVSE/NOPB Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 10 bits |
| Number of Channels | 2 (dual) |
| Architecture | Two-step / two-step flash |
| Tỷ lệ lấy mẫu | 20 MSPS (typical) / 30 MSPS (max) |
| Effective Number of Bits (ENOB) | 9.5 bits (over Nyquist) |
| Supply Voltage (Analog) | 3.0 V (single) |
| Digital I/O Supply Range | 1.5 V to 3.6 V |
| Power Consumption | 150 mW typical at 20 MSPS |
| Phạm vi điện áp đầu vào | 0.0 V to 2.0 V (with internal 2 Vpp reference) |
| Reference | Internal 1.0 V bandgap or external |
| Output Format | Straight binary or 2's complement, configurable |
| Output Mode | Parallel or multiplexed |
| Nhiệt độ hoạt động | -40C to +85C (industrial) |
| Hộp | 48-TQFP (7x7 mm), MS-026ABC |
| Kiểu lắp đặt | Surface Mount |
| Sample-and-Hold | Internal (per channel) |
Cấu hình chân ADC10D020CIVSE/NOPB
| Chân 1 | AVDD — Analog supply, 3.0 V |
| Chân 2 | VA1 — Analog input, channel 1 |
| Chân 3 | GND — Analog ground (pin 3 / pin 5 region) |
| Chân 4 | VA2 — Analog input, channel 2 |
| Chân 5 | GND — Analog ground |
| Chân 6 | VREF — Reference voltage (bypass) or external drive |
| Chân 7 | VBIAS — Bias voltage bypass |
| Chân 8 | VRT — Top reference (with internal divider) |
| Chân 9 | VRB — Bottom reference |
| Chân 10 | VD1 — Digital supply, channel 1 |
| Chân 11 | GND — Digital ground |
| Chân 12 | OD0 — Output data bit 0 (channel A) |
| Chân 13 | OD1 — Output data bit 1 |
| Chân 14 | OD2 — Output data bit 2 |
| Chân 15 | OD3 — Output data bit 3 |
| Chân 16 | OD4 — Output data bit 4 |
| Chân 17 | OD5 — Output data bit 5 |
| Chân 18 | OD6 — Output data bit 6 |
| Chân 19 | OD7 — Output data bit 7 |
| Chân 20 | OD8 — Output data bit 8 |
| Chân 21 | OD9 — Output data bit 9 (MSB) |
| Chân 22 | GND — Digital ground |
| Chân 23 | VD2 — Digital supply, channel 2 |
| Chân 24 | DCLK — Data output clock |
| Chân 25 | /OE — Output enable (active low) |
| Chân 26 | PD — Power-down control |
| Chân 27 | CLK — Sample clock input |
| Chân 28 | NC — Not connected (per datasheet) |
| Chân 29 | AVDD — Analog supply, 3.0 V (redundant) |
| Chân 30 | OVDD — Digital I/O supply, 1.5 V to 3.6 V |
| Chân 31 | GND — Ground |
| Chân 32 | NC — Not connected (per datasheet) |
| Chân 33 | TEST1 — Test pin (factory use, ground in normal operation) |
| Chân 34 | TEST2 — Test pin (factory use, ground in normal operation) |
| Chân 35 | FORMAT — Format select (binary / 2's complement) |
| Chân 36 | MODE — Mode select (parallel / multiplexed) |
| Chân 37 | GAIN — Gain select (1x / 1.5x) |
| Chân 38 | GND — Ground |
| Chân 39 | VD_DR — Driver supply for digital outputs |
| Chân 40 | OE_CH — Output enable for channel select |
| Chân 41 | GND — Ground |
| Chân 42 | AVSS — Analog substrate / ground |
| Chân 43 | VDD — Digital core supply |
| Chân 44 | GND — Ground |
| Chân 45 | V1A — Decoupling capacitor pin, channel 1 |
| Chân 46 | V2A — Decoupling capacitor pin, channel 2 |
| Chân 47 | GND — Ground |
| Chân 48 | AVDD — Analog supply |
Ứng dụng tiêu biểu
ADC10D020CIVSE/NOPB phù hợp cho 6 Áp dụngs: Ultrasound Imaging Front-End, Software-Defined Radio I/Q Digitizer, Portable Test & Measurement Instrumentation, CCD/CMOS Image Sensor Digitizers, Multi-Channel Oscilloscope Front-End, Industrial Process Control Data Acquisition.
Ultrasound Imaging Front-End
The ADC10D020CIVSE/NOPB's dual synchronized channels at 20 MSPS and 9.5 ENOB make it a classic dual-channel digitizer for ultrasound beamformer pre-beam analog-to-digital conversion. Each channel simultaneously samples an element of a transducer array with matched 150 mW power dissipation per pair, keeping per-channel thermal load manageable in dense arrays. Per TI's Typical Application circuits, an op-amp driver (such as OPA1632 or THS4631) feeds the VA inputs with 2 Vpp full-scale, while the /OE pin controls power-down between transmit pulses. Designers should note the 9.5 ENOB holds across the medical-grade input bandwidth of 1-15 MHz, supporting harmonic imaging modes in compact cart-based ultrasound. The 48-TQFP package also allows straightforward 4-channel expansion by stacking two ADC10D020 parts on a shared clock.
Được đề xuất
Software-Defined Radio I/Q Digitizer
In SDR receivers the ADC10D020CIVSE/NOPB's two channels are perfectly suited for sampling the I and Q baseband rails simultaneously, preserving phase and amplitude matching between paths. At 20 MSPS per channel it cleanly digitizes baseband signals up to about 7 MHz with the 9.5 ENOB required for 60+ dB SFDR. According to TI reference designs, the part's selectable straight-binary or 2's-complement output simplifies interfacing to the FPGA's quadrature decoder; the multiplexed output mode reduces pin count when used with FPGA high-speed LVDS interfaces. Power draw of 150 mW makes it attractive for portable tactical-radio and backpack SDR platforms where total link budget is constrained.
Được đề xuất
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data loggers benefit from the ADC10D020CIVSE/NOPB's dual 20 MSPS throughput combined with only 150 mW power, allowing two-channel digitizing front-ends on battery power. The split analog (3.0 V) and digital I/O (1.5 V to 3.6 V) supply rails enable direct connection to modern low-power FPGAs without level shifters, saving BOM cost. Per TI's datasheet electrical characteristics, the part achieves 9.5 ENOB at full Nyquist, sufficient for 60-dB SFDR measurement-grade instruments in the 1-10 MHz range. The parallel output mode yields deterministic latency critical for time-domain oscilloscope display alignment.
Được đề xuất
CCD/CMOS Image Sensor Digitizers
Dual-channel CCD line-scan cameras use the ADC10D020CIVSE/NOPB to digitize the analog video stream from two CCD outputs simultaneously, preserving registration accuracy between color channels. The 20 MSPS sampling rate matches typical 30 MHz-pixel-rate CCD outputs with margin for the analog front-end bandwidth limit. TI recommends the internal 1.0 V reference configuration when digitizing direct-coupled CCD outputs, eliminating a separate reference-voltage regulator. The 48-TQFP package provides solid thermal dissipation for the 150 mW continuous load typical in machine-vision line-scan cameras mounted in industrial gantries.
Được đề xuất
Multi-Channel Oscilloscope Front-End
Digital storage oscilloscopes and bench-top data-acquisition systems often pair two ADC10D020CIVSE/NOPB devices to digitize 4 channels simultaneously at 20 MSPS, providing cost-effective multi-channel digitizing in a single PCB quadrant. The IC's separate analog 3.0 V and digital 1.5-3.6 V supply rails simplify isolation between the analog front-end and FPGA bus voltages. The internal sample-and-hold and offset-correction circuits reduce external analog conditioning requirements, supporting compact 4-layer PCB designs. Per TI datasheet Figure 'Typical Application', adding a 10 uF tantalum + 0.1 uF ceramic decoupling pair at AVDD/AVDD2 pins maintains the rated 9.5 ENOB across full sample rate.
Được đề xuất
Industrial Process Control Data Acquisition
Industrial PLCs, motor-control feedback boards, and multi-loop process controllers use the ADC10D020CIVSE/NOPB for high-speed synchronized current/voltage sensing on multiple phases, critical for field-oriented control (FOC) of three-phase motor drives. The 20 MSPS throughput exceeds typical 5-10 kHz FOC control loops, providing wide loop margin for advanced control algorithms. Per the TI datasheet's industrial temperature grade, the part operates from -40C to +85C without derating, suitable for unenclosed factory-floor enclosures. Selectable straight-binary or 2's-complement digital output eases integration with both legacy 5 V DSPs and modern 1.8 V MCUs.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADC10D020CIVSE/NOPB — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADC10D020CIVS/NOPB | ADC10D020CIVSX/NOPB | ADC10D040CIVSE/NOPB | ADC10D020CISQ/NOPB | ADC12D040CIVY/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (7x7) | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same | 48-TQFP (7x7) - same |
| Resolution (bits) | 10 | 10 | 10 | 10 | 10 | 12 (+20%) |
| Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Sampling Rate (MSPS) | 20 (30 max) | 20 | 20 | 40 (+100%) | 20 | 40 (+100%) |
| Power Consumption | 150 mW typical | 150 mW | 150 mW | ~200 mW (+33%) | 150 mW | ~275 mW (+83%) |
| ENOB (Nyquist) | 9.5 bits | 9.5 bits | 9.5 bits | 9.4 bits | 9.5 bits | 11.0 bits |
| Architecture | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 10-bit | Two-step / dual 12-bit |
| Supply Voltage (Analog) | 3.0 V | 3.0 V | 3.0 V | 3.0 V | 3.0 V | 3.0 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Bảo phân biệt quan trọng
- Same die and pinout as CIVS/NOPB - zero-risk drop-in path (vsADC10D020CIVS/NOPB)
- Pin-compatible upgrade path to 40 MSPS (vsADC10D040CIVSE/NOPB)
- 12-bit pin-compatible upgrade for higher dynamic range (vsADC12D040CIVY/NOPB)
- Split analog/digital supply simplifies low-voltage FPGA interface (vsSingle-supply 10-bit ADCs)
Ghi chú thiết kế
Estimated: For best 9.5 ENOB performance, place the analog supply 3.0 V and digital I/O supply decoupling as close as possible to the package - place a 10 uF tantalum within 5 mm of AVDD pin and a 0.1 uF ceramic on every AVDD/DVDD pin. Use a single-point star ground tying all analog grounds (multiple GND pins) and digital grounds at one location near the ADC. The estimated loop inductance at 5 mm trace and 100 nH/in is small enough to suppress the 20 MHz fundamental switching noise in the 150 mW class converters.
Estimated: Route the differential CLK input as a matched pair (input: clock driver placed within 10 mm of CLK pin, 50-ohm controlled impedance) to preserve timing margin at 20 MSPS. If the source is single-ended, use a low-jitter 3.3 V to 3.0 V translator (74AVC or similar) feeding a center-tapped transformer for the CLK pin. Estimated jitter contribution at 30 MSPS from a 50 ps rms clock yields SNR degradation only ~1 dB at 9.5 ENOB; aim for < 5 ps rms for headroom.
Estimated: At 150 mW continuous power in a 48-TQFP package (theta_JA ~50 C/W on a 4-layer JEDEC test board), junction temperature rise is approximately 7.5 C above ambient (7.5 C = 0.150 W * 50 C/W). This is within the -40C to +85C industrial specification with no derating required. If forced-air cooling is used in tight enclosures, ensure airflow path is not blocked by nearby FPGAs that share the same heat-sinking strategy.
Critical pitfall: do NOT drive VA1 / VA2 with single-ended signals exceeding the VRT/VRB common-mode window; the part assumes 2 Vpp differential centered around 1.0 V (mid-reference). Per TI datasheet Absolute Maximum Ratings, VA inputs must stay within AVDD+0.3 V and AVSS-0.3 V. Failing to AC-couple or DC-bias into the recommended input window causes distortion degradation well below datasheet's 9.5 ENOB. Use OPA1632 or THS4631 differential driver for full-spec performance.
Thông tin tuân thủ
/NOPB suffix denotes Pb-free / RoHS-compliant per TI ordering guide. Industrial temperature grade -40C to +85C. AEC-Q100 not applicable (consumer/industrial ADC, not automotive qualified).
