ADS805E - 12-Bit 20-MSPS Pipelined ADC | Texas Instruments
MPN： ADS805E ✓ 啟用中ADS805E 概覽
An ADC is a data-acquisition integrated circuit that samples an analog voltage and converts it into a digital code for processing, storage, or transmission. More specifically, the ADS805E belongs to the pipelined ADC family, which uses multiple internal stages to support high conversion rates. Its 12-bit resolution represents each sample with 4,096 digital codes, while its 20-MSPS sampling capability supports bandwidths below the converter's Nyquist limit when appropriate analog filtering and clock design are used.
Key features include one analog input, pipelined 12-bit conversion, internal or external reference support, and selectable input ranges. The 2 Vp-p range is identified in the manufacturer information as easy to drive with a single operational amplifier and as providing the best spurious performance. The converter's 74 dB SFDR and 68 dB SNR indicate strong performance for communications, imaging, and test-instrumentation signal chains, while the stated 300 mW power level helps guide thermal and supply planning.
The ADS805 architecture combines a high-bandwidth track-and-hold circuit with pipelined stages. The high-bandwidth track-and-hold minimizes acquisition-time effects, while low jitter and linear sampling behavior help preserve signal fidelity. The flexible input range allows the system designer to trade signal amplitude against dynamic range and gain requirements. The ADC should be paired with a clean analog supply, a suitable clock source, input protection, and filtering matched to the intended bandwidth.
Typical applications include studio cameras, IF and baseband digitization, copiers, communications receivers, video signal acquisition, and test instrumentation. In each case, the 20-MSPS rate allows sampling above the signal bandwidth, while the 12-bit code width and reported dynamic performance provide a practical balance between resolution, speed, and integration complexity. The ADS805E is particularly suitable when the existing board already expects the 28-pin SSOP footprint and the associated pin-compatible family arrangement.
Designers should verify the exact package, pinout, reference configuration, input range, and timing requirements against the manufacturer datasheet before layout release. Pay attention to analog input bandwidth, settling time, clock jitter, reference noise, and output interface implementation. The most important design trade-off is ensuring that the input driver and external network do not degrade the converter's measured noise and spurious-free dynamic-range performance.
This page consolidates the verified ADS805E product identity, distributor listings, manufacturer family data, pin-compatibility evidence, and practical application guidance. It is designed to help engineers evaluate the converter for procurement and board-level design without treating unsupported specifications as confirmed facts.
直接替換替代品，適用於 ADS805E — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS805E （相同外形與佔位） — 差異在於 Operating Temperature, Package, Reference, Architecture, Resolution.
ADS804E
✅ 直接替換聯絡詢價
查看資料表 →ADS803E/1KG4
✅ 直接替換聯絡詢價
查看資料表 →ADS805EG4
✅ 直接替換📋 參考替代品（不在目錄中）
ADS805E 最大額定值與電氣特性
| 解析度 | 12 bit |
| Conversion Rate | 20 MSPS |
| Architecture | Pipelined ADC |
| Input Count | 1 input |
| Analog Input Range | 2 Vp-p to 5 Vp-p |
| Reference | Internal or external reference |
| Spurious-Free Dynamic Range | 74 dB |
| Signal-to-Noise Ratio | 68 dB |
| Differential Nonlinearity | 0.25 LSB |
| Power Consumption | 300 mW |
| 封裝 | 28-pin SSOP |
| 工作溫度 | -40°C to 85°C |
| 介面 | Parallel digital ADC output |
| Sampling Architecture | High-bandwidth track-and-hold |
ADS805E 28-pin ssop 腳位配置指南
ADS805E（28-pin ssop 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADS805E.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADS805E 適用於 6 應用s: Communications IF and Baseband Digitization, Studio Camera Video Conversion, Copier and Document Imaging, Test and Measurement Instrumentation, Video Signal Acquisition, Communications Receiver Front Ends.
Communications IF and Baseband Digitization
The Texas Instruments ADS805E fits communications IF and baseband digitization because it combines a 20-MSPS conversion rate with 12-bit resolution, 74 dB SFDR, and 68 dB SNR. It can sample an intermediate-frequency or baseband waveform when the signal bandwidth is appropriate and the front end provides controlled gain and filtering. The 2 Vp-p mode is specifically identified as easy to drive with one operational amplifier, which can simplify a compact receiver front end. Designers should still prioritize low-jitter clocking, clean reference routing, and an anti-alias filter because the converter's published dynamic performance depends on the complete analog and clock system.
推薦
Studio Camera Video Conversion
ADS805E is suitable for studio-camera video conversion where a compact 12-bit, 20-MSPS ADC can sample video-related analog signals. The device's reported 74 dB SFDR and 68 dB SNR provide useful headroom for acquisition systems that must preserve low-level signal details while rejecting harmonics and spurious products. The selected input range can be matched to the camera's analog drive level, with the 2 Vp-p setting offering a straightforward single-op-amp interface according to TI. PCB layout must keep the analog path short and provide a stable reference, while the digital output path must be routed according to the converter's timing and interface requirements.
推薦
Copier and Document Imaging
The ADS805E can support copier and document-imaging acquisition paths requiring moderate-speed analog digitization at 12-bit resolution. A 20-MSPS converter is useful when the sensor or preamplifier produces a bandwidth that requires oversampling or when the system benefits from faster acquisition than the final image-processing rate. The flexible 2 Vp-p to 5 Vp-p input range allows the analog board to normalize sensor amplitude, while the reported 68 dB SNR supports quality-sensitive measurements. Engineering validation should confirm sensor drive bandwidth, settling behavior, connector and ground strategy, and the exact digital timing needed by the downstream image processor.
推薦
Test and Measurement Instrumentation
ADS805E is appropriate for instrumentation that must capture repetitive analog waveforms with 12-bit resolution and a 20-MSPS sampling rate. The published 74 dB SFDR and 68 dB SNR make it useful when the instrument needs adequate dynamic range for signal characterization rather than only basic threshold sensing. The converter can be preceded by a gain and anti-alias network, followed by a processor or FPGA that consumes its digital samples. Calibration should include offset, gain, reference noise, clock-jitter, and bandwidth checks. Because the supplied data does not state output coding, supply limits, or a full timing table, those items must be verified from the manufacturer datasheet.
推薦
Video Signal Acquisition
The ADS805E can be used in video signal-acquisition systems when 20-MSPS sampling and 12-bit code resolution fit the source bandwidth. The flexible input range lets the analog front end match signal amplitude, and the manufacturer's stated 2 Vp-p mode simplifies single-op-amp drive while supporting low spurious performance. A practical design should use short analog traces, a low-noise reference, a clock with adequate phase noise, and an anti-alias filter matched to the video bandwidth. The converter's parallel output must be connected according to the verified package pinout and timing requirements, which should be obtained from the official datasheet before PCB release.
推薦
Communications Receiver Front Ends
ADS805E is a good candidate for receiver front ends that need deterministic sampling of an analog communications waveform. Its 20-MSPS rate supports Nyquist-based architecture decisions, while the 12-bit resolution and reported 68 dB SNR provide useful signal fidelity. The analog input range can be selected according to the receiver's gain plan, and the 2 Vp-p option is documented as suitable for a single-op-amp drive. The key performance risk is clock and reference noise: use a low-jitter clock, isolate sensitive routes, place decoupling near the converter, and verify analog settling at the highest supported input frequency before production.
推薦
推薦產品摘要
工程參考資料，適用於 ADS805E — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS804E | ADS803E | ADS805EG4 |
|---|---|---|---|---|
| Package | 28-SSOP | 28-SSOP family package; verify exact suffix package | 28-SSOP family package; verify exact suffix package | 28-SSOP family package; verify exact suffix package |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Conversion Rate | 20 MSPS | 10 MSPS | 5 MSPS | 20 MSPS family specification |
主要差異化特點
- Higher conversion rate than the verified ADS804 family alternative (對比ADS804E)
- Higher conversion rate than the verified ADS803 family alternative (對比ADS803E)
- Published dynamic-performance figures (對比ADS804E)
- Flexible analog input configuration (對比ADS803E)
設計說明
Keep the analog input route short and place the input network close to the ADS805E analog input. The converter's reported 74 dB SFDR is sensitive to the complete signal path, including op-amp bandwidth, settling, source impedance, and parasitic capacitance. Use the manufacturer's recommended input network and verify the 2 Vp-p mode with the actual driver because the input capacitance and reference configuration can alter settling and spurious performance.
Use the verified 300 mW device-power figure as the starting point for supply budgeting, then confirm actual dissipation from the selected supply voltage, reference mode, clock rate, and output loading in the datasheet. Place bypass capacitors at the appropriate supply pins, maintain a low-impedance return path, and isolate analog and digital return currents where the layout guidance permits. The supplied data does not include supply-voltage limits, so do not select a regulator rail without checking the manufacturer documentation.
Route the sampling clock as a controlled, short signal and avoid routing it beneath noisy analog or switching nodes. Clock jitter directly affects conversion-time uncertainty, especially when sampling a high-frequency communications or video waveform. Keep the clock source, reference, analog input, and digital outputs physically organized, and use the official package pinout and layout example before releasing copper because the complete 28-pin mapping was not included in the verified search data.
Do not substitute ADS804E or ADS803E automatically when a design requires the ADS805E's 20-MSPS rate. TI identifies them as pin-compatible with the ADS805 family, but their verified conversion rates are 10 MSPS and 5 MSPS respectively. Check Nyquist margin, acquisition time, clock timing, output latency, reference behavior, and analog performance before treating either device as a drop-in replacement.
合規資訊
The supplied verified search data identifies the manufacturer, package, electrical highlights, distributor listings, and TI family pin-compatibility statement, but it does not provide specific RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals declarations.