ADS803E/1KG4 - 12-Bit 5MSPS ADC w/ Int/Ext Ref | Texas Instruments
MPN： ADS803E/1KG4 ✓ 啟用中ADS803E/1KG4 概覽
A pipelined ADC is a type of analog-to-digital converter that resolves each analog sample across multiple low-resolution stages, with each stage feeding its residue to the next clock cycle. This pipeline architecture enables high throughput (MSPS-class) at moderate die area, making pipelined ADCs the workhorse of high-speed data acquisition, communications, video, medical imaging, and test instrumentation. The ADS803E/1KG4 sits in the broader hierarchy of: ADC -> data converter -> signal chain IC -> semiconductor.
Key differentiating specifications include a programmable 2 Vp-p or 5 Vp-p input range, internal or external reference option, TTL/CMOS-compatible digital outputs, and differential linearity that supports demanding imaging applications. Digital error-correction techniques ensure excellent DNL (differential non-linearity), while the low distortion and high SNR provide the extra margin needed for communications and video signal chains.
The ADS803E/1KG4 architecture uses a multi-stage switched-capacitor pipeline with digital error correction, achieving true 12-bit performance at 5 MSPS without the latency penalty of successive-approximation (SAR) ADCs. Its single +5V analog supply simplifies power-tree design versus split-rail converters, and the differential analog input rejects common-mode noise from upstream sensor or driver stages.
Typical applications include medical imaging front-ends, communications baseband IF sampling, CCD/CMOS image sensor digitizers, video digitizing, and test-and-measurement instrumentation where 12-bit resolution at 5 MSPS is sufficient. The 28-SSOP footprint is also a near-universal upgrade path to the ADS804 (10 MSPS) and ADS805 (20 MSPS) for future-proof designs.
When designing with this converter, ensure the analog input common-mode voltage stays within the specified range, place a small RC anti-aliasing filter at AINP/AINN, and decouple AVDD and DVDD with separate 0.1 uF + 10 uF ceramic capacitors close to the pins. The internal reference eliminates an external reference IC in cost-sensitive designs; for best DC accuracy use an external 2.500V reference. According to TI, the digital outputs can drive TTL and CMOS loads directly without external buffers below 5 pF.
This page synthesizes distributor pricing, drop-in alternatives from the TI ADS80x family, and PCB design notes that go beyond the manufacturer datasheet - including thermal and reference-decoupling guidance not found on TI.com.
直接替換替代品，適用於 ADS803E/1KG4 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS803E/1KG4 （相同外形與佔位） — 差異在於 Operating Temperature, Package, Reference, Power Consumption, Sampling Rate.
ADS803E
✅ 直接替換聯絡詢價
查看資料表 →ADS803EG4
✅ 直接替換📋 參考替代品（不在目錄中）
ADS804E/1K
✅ 直接替換📋 參考替代品（不在目錄中）
ADS805E/1KG4
✅ 直接替換聯絡詢價
查看資料表 →ADS803E/1KG4 最大額定值與電氣特性
| 解析度 | 12 bits |
| Sample Rate | 5 MSPS |
| Number of Inputs | 1 (single-ended/differential) |
| Architecture | Pipelined |
| 輸入電壓範圍 | 2 Vp-p (programmable, 5 Vp-p option) |
| Reference | Internal 2.5V or external |
| Supply Voltage (Analog) | 5 V single supply |
| Supply Voltage (Digital) | 5 V (AVDD = DVDD) |
| 工作溫度 | -40C to +85C (industrial) |
| 封裝 | 28-SSOP |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant (G4 suffix denotes Pb-free) |
| Input Type | Differential analog |
| Output Interface | Parallel, TTL/CMOS-compatible |
| Temperature Grade | Industrial |
ADS803E/1KG4 腳位配置
| 腳位 1 | AINP — Differential analog input, positive |
| 腳位 2 | AINN — Differential analog input, negative |
| 腳位 3 | REFBSET — Reference bias / external bypass |
| 腳位 4 | REFIN — External reference input (if used) |
| 腳位 5 | REFOUT — Internal 2.5V reference output |
| 腳位 6 | AGND — Analog ground |
| 腳位 7 | AVDD — Analog +5V supply |
| 腳位 8 | DVDD — Digital +5V supply |
| 腳位 9 | DGND — Digital ground |
| 腳位 10 | OE — Output enable (active low) |
| 腳位 11 | CLK — Sampling clock input |
| 腳位 12 | NC — Not connected (per datasheet) |
| 腳位 13 | DB11 — Data bit 11 (MSB) |
| 腳位 14 | DB10 — Data bit 10 |
| 腳位 15 | DB9 — Data bit 9 |
| 腳位 16 | DB8 — Data bit 8 |
| 腳位 17 | DB7 — Data bit 7 |
| 腳位 18 | DB6 — Data bit 6 |
| 腳位 19 | DB5 — Data bit 5 |
| 腳位 20 | DB4 — Data bit 4 |
| 腳位 21 | DB3 — Data bit 3 |
| 腳位 22 | DB2 — Data bit 2 |
| 腳位 23 | DB1 — Data bit 1 |
| 腳位 24 | DB0 — Data bit 0 (LSB) |
| 腳位 25 | NC — Not connected (per datasheet) |
| 腳位 26 | RANGE — Input range select (2Vp-p or 5Vp-p) |
| 腳位 27 | STBY — Standby mode (active high) |
| 腳位 28 | AGND — Analog ground |
典型應用
ADS803E/1KG4 適用於 6 應用s: Medical Imaging Front-End, Communications Baseband Digitizing, CCD/CMOS Image Sensor Digitizer, Video Digitizing, Test and Measurement Instrumentation, Industrial Process Control Data Acquisition.
Medical Imaging Front-End
The ADS803E/1KG4's 12-bit resolution at 5 MSPS with digital-error-corrected pipelined architecture is well matched to ultrasound and endoscopy front-ends that digitize 5 MHz-class IF signals. Its 2.5V internal reference and differential analog input reject common-mode noise from upstream LNA stages, while the industrial -40C to +85C temperature grade supports operating-room equipment. Designers should pair the converter with a low-noise front-end op-amp, place 0.1 uF+10 uF ceramic decoupling on AVDD/DVDD, and accept the 5 MSPS cap as adequate for sub-2 MHz baseband imaging. Same-family TI ADS804/ADS805 upgrades enable future throughput scaling on the same PCB.
推薦
Communications Baseband Digitizing
Where a 5 MHz IF signal chain feeds a DSP, the ADS803E/1KG4 provides 12-bit dynamic range at 5 MSPS - sufficient for narrow-band baseband receivers in proprietary radio and telemetry links. Digital error correction preserves DNL under demanding modulation, and the TTL/CMOS output bus connects directly to a CPLD or DSP data port without external buffers below 5 pF. Compare against the ADS804E/1KG4 (10 MSPS) on the same PCB if your channel bandwidth grows; the SSOP-28 pinout stays identical so no layout rework is needed.
推薦
CCD/CMOS Image Sensor Digitizer
For video-rate digitizing of CCD or CMOS image sensor outputs the ADS803E/1KG4's pipelined architecture captures single-shot frames at low latency, and the programmable 2 Vp-p input range matches typical image-sensor full-scale outputs. Excellent differential linearity supports demanding imaging pipelines where pixel-level gradients must be preserved across frames. The 28-SSOP footprint is shared with the pin-compatible ADS805E (20 MSPS), letting the same PCB accept HD-rate video streams if your camera design scales up later. Designers should isolate analog and digital grounds and use a low-jitter clock for best SNR.
推薦
Video Digitizing
Standard-definition video digitizers typically run at 10-20 MSPS, so the ADS803E/1KG4 covers compressed video and CCTV streams, while the pin-compatible ADS804E and ADS805E provide headroom for full SDTV rates on the same PCB. The pipelined architecture delivers low-latency single-cycle acquisition suitable for real-time video processing. Designers should keep analog traces short and routed over a continuous ground plane; the SSOP-28 pinout's REFIN/REF pins require a 0.1 uF+10 uF local bypass. Use the internal 2.5V reference for cost-sensitive consumer video gear.
推薦
Test and Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and data-acquisition cards use the ADS803E/1KG4 to digitize repetitive waveforms where 12-bit vertical resolution and 5 MSPS real-time rate balance price and performance. Low distortion and high SNR give the extra dynamic-range margin critical for harmonic and intermodulation measurements. The parallel CMOS output bus interfaces cleanly with an FPGA capture FIFO; engineers should provide a low-jitter sampling clock and maintain 50-ohm-controlled-impedance analog traces for repeatable measurements.
推薦
Industrial Process Control Data Acquisition
For multi-channel industrial data-acquisition systems the ADS803E/1KG4's industrial temperature grade (-40C to +85C) and single +5V supply handle factory-floor noise and temperature swings. Its pipelined architecture gives higher throughput than SAR ADCs while keeping per-channel cost low, making it suitable for vibration monitoring, motor-control feedback, and process-sensor digitizers. Team the converter with an analog mux for channel expansion; isolate digital and analog grounds, and use wide PCB traces for the analog supply to minimize voltage-drop on AVDD under 5 MSPS bursts.
推薦
推薦產品摘要
工程參考資料，適用於 ADS803E/1KG4 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS803E | ADS803EG4 | ADS804E/1K | ADS805E/1KG4 | ADS804E | ADS805E |
|---|---|---|---|---|---|---|---|
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Sample Rate | 5 MSPS | 5 MSPS | 5 MSPS | 10 MSPS (+100%) | 20 MSPS (+300%) | 10 MSPS | 20 MSPS |
| Resolution | 12-bit | 12-bit | 12-bit | 12-bit | 12-bit | 12-bit | 12-bit |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Input Range | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable | 2 Vp-p or 5 Vp-p programmable |
| Reference | Internal 2.5V or external | Internal 2.5V or external | Internal 2.5V or external | Internal 2.5V or external | Internal 2.5V or external | Internal 2.5V or external | Internal 2.5V or external |
| Temperature Grade | Industrial -40C to +85C | Industrial | Industrial | Industrial | Industrial | Industrial | Industrial |
| Pin-to-Pin Compatibility | Family base (5 MSPS) | Yes | Yes | Yes (10 MSPS upgrade) | Yes (20 MSPS upgrade) | Yes | Yes |
主要差異化特點
- Pin-compatible family scalability (對比ADS805E/1KG4)
- Lowest-cost member of TI ADS80x pin-compatible family (對比ADS804E/1K)
- Internal 2.5V reference eliminates external reference IC (對比AD9224 (Analog Devices, not pin-compatible))
設計說明
The ADS803E/1KG4 requires a clean analog +5V (AVDD) and digital +5V (DVDD) supply. Place a 0.1 uF X7R ceramic bypass as close as possible to each supply pin, with a bulk 10 uF tantalum or aluminum-polymer cap nearby. Per the TI reference design, separate AVDD and DVDD with ferrite beads to prevent digital switching noise from corrupting the analog substrate - this is critical at 5 MSPS where fast output transitions cause significant transient current on DVDD.
Use a continuous analog ground plane under the AINP/AINN, REFIN, REFOUT and AGND pins; do not split the ground plane underneath the converter. Route the sampling clock (CLK) with controlled 50-ohm impedance and keep it away from analog input traces by at least 3x their width. Per the TI layout checklist in the datasheet, place the reference decoupling cap directly between REFOUT and the nearest AGND via - long traces here will degrade SNR by several dB.
Two common pitfalls when using the ADS803E/1KG4: (1) Driving AINP/AINN below the allowed common-mode range will cause severe SNR degradation; add a coupling transformer or DC-bias network. (2) Exceeding 5 Vp-p input range with the RANGE pin tied high can saturate the front-end; verify your sensor output amplitude and select RANGE accordingly. Always deassert OE during power-up to keep outputs high-impedance until the supply settles.
合規資訊
The /1KG4 suffix denotes lead-free (Pb-free, G4) shipping. RoHS compliance per Texas Instruments product page. Industrial temperature grade; not AEC-Q100 qualified.