ADS804E - 12-Bit 10-MSPS Pipelined ADC | Texas Instruments
MPN： ADS804E ✓ 啟用中ADS804E 概覽
An ADC is an integrated circuit that converts an analog voltage into a digital code. A pipelined ADC uses multiple internal stages and parallel output data, allowing a higher conversion rate than many single-stage architectures. The ADS804E belongs to the ADC and data-converter hierarchy, where resolution, sampling rate, input range, reference accuracy, interface timing, and noise performance determine suitability.
The ADS804E combines 12-bit resolution with a 10 MSPS sampling rate. Verified distributor and manufacturer listings identify the device as a one-input pipelined converter with a flexible 2 Vp-p input range, internal and external reference options, 80 dB SFDR at Nyquist, 69 dB SNR, 180 mW low power, and differential linearity of ±0.3 LSB. These figures make it appropriate for IF and baseband digitization, CCD imaging, scanners, and test instrumentation.
The device uses a high-bandwidth track-and-hold stage to minimize acquisition-related error and maintain useful performance at higher input frequencies. Its parallel interface supports straightforward connection to digital logic, FPGA input blocks, DSPs, or data-capture systems. The internal reference can simplify system design, while external-reference operation can be useful when multiple converters must share a precision reference or when calibration requirements demand tighter reference control.
Typical implementations include communications receivers, industrial measurement systems, imaging equipment, laboratory instruments, and embedded data-acquisition platforms. The 10 MSPS rate allows the converter to capture rapidly changing waveforms, while 12-bit resolution provides 4096 digital codes for the selected analog input range.
Designers should pay close attention to input common-mode voltage, analog signal amplitude, reference stability, source impedance, clock jitter, and the timing relationship between acquisition, conversion, and parallel output. The manufacturer datasheet should be consulted for the complete pinout, timing diagrams, input-range configuration, electrical limits, and recommended application circuit. This page combines verified manufacturer and distributor information with engineering guidance, application context, and comparison notes to support component selection and PCB planning.
直接替換替代品，適用於 ADS804E — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS804E （相同外形與佔位） — 差異在於 Operating Temperature, Package, Reference, Sampling Rate, Power Consumption.
ADS803E/1KG4
✅ 直接替換聯絡詢價
查看資料表 →ADS805E/1KG4
✅ 直接替換聯絡詢價
查看資料表 →ADS804E/1K
✅ 直接替換📋 參考替代品（不在目錄中）
ADS804EG4
✅ 直接替換📋 參考替代品（不在目錄中）
ADS804E 最大額定值與電氣特性
| 解析度 | 12 bits |
| 取樣率 | 10 MSPS |
| Architecture | Pipelined ADC |
| Number of Inputs | 1 input |
| 輸入電壓範圍 | 2 Vp-p programmable range |
| Reference | Internal or external |
| Output Interface | Parallel |
| Spurious-Free Dynamic Range | 80 dB at Nyquist |
| Signal-to-Noise Ratio | 69 dB |
| Power Consumption | 180 mW |
| Differential Linearity | ±0.3 LSB |
| 封裝 | 28-pin SSOP |
| 工作溫度 | -40°C to +85°C |
| Overrange Indicator | Available |
| Track-and-Hold | High-bandwidth track-and-hold |
ADS804E 28-pin ssop 腳位配置指南
ADS804E（28-pin ssop 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADS804E.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADS804E 適用於 6 應用s: IF and Baseband Communications Digitization, CCD Imaging and Scanner Digitization, Test and Measurement Instrumentation, Industrial Data Acquisition, RF and Baseband Receiver Front Ends, FPGA-Based Digital Capture.
IF and Baseband Communications Digitization
The ADS804E fits IF and baseband communications digitization because it combines a 10 MSPS sampling rate with 12-bit resolution and a high-bandwidth track-and-hold stage. Use it when a receiver needs to convert an intermediate-frequency or baseband waveform into parallel digital data for filtering, demodulation, or digital correction. Its verified 80 dB SFDR at Nyquist and 69 dB SNR are important for preserving signal-to-noise performance, while the flexible 2 Vp-p input range allows the analog front end to select a suitable signal scale. Clock jitter, source impedance, and input-driver settling must still be controlled.
推薦
CCD Imaging and Scanner Digitization
The ADS804E is suitable for CCD imaging, scanners, and other sensor-digitization systems that require consistent sampling of rapidly changing analog outputs. The 10 MSPS rate provides temporal resolution for motion or scan-rate requirements, while the 12-bit converter supplies 4096 digital levels. A high-bandwidth track-and-hold stage can help acquire the sensor waveform during the sampling interval. In a scanner design, use a suitable input buffer, define the analog common-mode level, and route the 12-bit parallel bus with timing margin to an FPGA or digital controller.
推薦
Test and Measurement Instrumentation
ADS804E can be used in oscilloscope-like, waveform-capture, and automated test equipment when a 10-MSPS, 12-bit measurement path is sufficient. Its parallel output allows direct connection to an FPGA capture engine, and the overrange indicator can assist with input-range detection. The 69 dB SNR specification is useful for preserving small-signal detail, but system accuracy also depends on reference quality, analog gain, input bandwidth, and calibration. For laboratory-grade measurements, define calibration points and ensure the selected external or internal reference remains stable during the measurement interval.
推薦
Industrial Data Acquisition
The ADS804E supports industrial acquisition systems that digitize sensor outputs or conditioned process signals at up to 10 MSPS. The single-input architecture is appropriate when each converter is paired with one analog channel, and the flexible input range can simplify front-end scaling after conditioning. The converter's parallel output is useful for FPGA-based filtering, event detection, or real-time control. Industrial systems should pay attention to grounding, isolation, clock distribution, and power-supply noise; these factors can affect SNR and SFDR more than the nominal converter specification.
推薦
RF and Baseband Receiver Front Ends
ADS804E is suitable for digitizing conditioned RF or IF signals when the design requires a 10 MSPS, 12-bit conversion stage. The device should follow the RF front end rather than directly connect to a high-frequency RF node; the analog input driver must provide appropriate gain, filtering, impedance, and common-mode behavior. Verified performance figures of 80 dB SFDR at Nyquist and 69 dB SNR help characterize the converter, while the flexible input range supports scaling after mixer or amplifier stages. PCB layout should keep the analog path short and separate high-current clock and digital-return paths.
推薦
FPGA-Based Digital Capture
ADS804E is well matched to an FPGA capture architecture because it delivers 12-bit parallel output at 10 MSPS. The FPGA can capture code words, perform thresholding or filtering, and transfer only relevant events to a host processor, reducing host data traffic. Because the ADC requires accurate sampling timing, the clock relationship between the converter and FPGA must be budgeted with setup and hold margin. The analog input and reference should be decoupled close to the device, and the parallel data bus should be routed with controlled length and return-path continuity.
推薦
推薦產品摘要
工程參考資料，適用於 ADS804E — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS803 | ADS805 | ADS804E/1K | ADS804EG4 |
|---|---|---|---|---|---|
| Sampling Rate | 10 MSPS | 5 MSPS | 20 MSPS | 10 MSPS | 10 MSPS |
| Package | 28-pin SSOP | 28-pin SSOP | 28-pin SSOP | 28-pin SSOP | 28-pin SSOP |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
主要差異化特點
- Mid-speed sampling rate within the pin-compatible ADS803 and ADS805 family (對比ADS803)
- Lower sampling rate than the faster ADS805 family member (對比ADS805)
- 12-bit parallel conversion with verified dynamic-performance figures (對比ADS804EG4)
設計說明
The ADS804E is listed at 180 mW, so provide a clean, low-noise analog and digital supply network with local decoupling close to the device. Separate the sensitive analog reference and input returns from switching and clock-return currents where possible. The verified data does not provide complete supply-voltage limits, capacitor values, or ESR requirements; use the Texas Instruments ADS804 datasheet and application guidance for final values and stability recommendations.
Keep the analog input path short and place the input driver and any recommended anti-alias filtering close to the ADC. The 10 MSPS sampling rate does not remove the need for controlled source impedance, settling time, and impedance matching. Route the 12-bit parallel output with continuous return paths, and match clock and data timing to the receiver FPGA or DSP. Confirm timing margins against the manufacturer timing diagrams.
Do not treat pin compatibility as automatic electrical equivalence. ADS803 is identified as a 5 MSPS family member and ADS805 as a 20 MSPS member, so replacing ADS804E can change acquisition time, clock requirements, power, bandwidth, and system timing. Before substitution, verify input range, reference polarity and voltage, output coding, pin names, supply levels, clock phase, and acquisition timing against the relevant datasheet.
Use a short, controlled-impedance analog input route and keep the reference distribution quiet and well decoupled. Avoid routing high-current digital or switching signals beneath the analog input and reference nets. The parallel output bus should be length-matched only as required by the actual receiver timing, while the clock should be distributed cleanly to maintain low jitter. The supplied verified data does not include a manufacturer PCB layout, so follow the TI ADS804 datasheet and reference guidance for final placement.
合規資訊
The supplied verified data does not explicitly state RoHS, REACH, lead-free, halogen-free, conflict-minerals, or AEC-Q100 status. Compliance must be confirmed from the current manufacturer product documentation or supplier certificates.