EP2C35F672I6N - 33,216 Logic Cells Cyclone II FPGA | Intel
MPN： EP2C35F672I6N ✗ 停產EP2C35F672I6N 概覽
A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit built around a matrix of configurable logic blocks (CLBs) connected via programmable interconnect. FPGAs occupy a unique position between general-purpose processors (CPUs/MCUs) and application-specific integrated circuits (ASICs): they offer hardware-level parallelism and deterministic timing like ASICs but remain re-programmable, making them ideal for prototyping, low-volume production, and designs requiring late-stage hardware changes. Within the broader taxonomy, the EP2C35 sits in the low-cost, high-volume Cyclone II family, which itself belongs to the programmable logic device (PLD) category of digital ICs.
Key differentiating specifications include 4 embedded PLL blocks for clock management, support for multiple I/O standards (LVDS, LVTTL, LVCMOS, SSTL, HSTL, PCI), and a 1.2V core supply (1.15V to 1.25V) with a separate 3.3V I/O supply. The device operates across the industrial temperature range of -40C to +100C (the 'I' suffix) and the speed grade 6 designation places it in the mid-tier performance bucket. The 672-ball BGA package supports up to 322 user I/O pins, making the EP2C35 one of the densest members of the Cyclone II family.
The Cyclone II architecture combines a low-k dielectric 90nm process with a logic structure optimized for DSP and consumer applications. Its 18x18 multiplier blocks enable single-cycle multiply-accumulate operations, while the M4K memory blocks can be configured as RAM, ROM, or FIFO with byte enables. This combination makes the EP2C35F672I6N particularly well-suited for parallel DSP pipelines where multiple MAC operations must complete in a single clock cycle.
Typical applications include digital video processing, software-defined radio baseband, industrial motor control, low-cost ASIC prototyping, and embedded vision systems. The wide I/O count supports parallel data buses for SDRAM, SRAM, and video ADCs/DACs without external bus multiplexing.
When designing with this part, pay close attention to the four PLL configuration constraints and bank-based I/O voltage grouping. The 672-ball BGA requires a 4-layer or better PCB stack-up with controlled-impedance routing and a solid ground pour beneath the device to meet signal-integrity requirements for LVDS interfaces.
This page synthesizes distributor pricing, pin-compatible Cyclone II drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替換替代品，適用於 EP2C35F672I6N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP2C35F672I6N （相同外形與佔位） — 差異在於 Process Technology, Operating Temperature, Package, Speed Grade, RoHS Status.
EP2C35F672C6N
✅ 直接替換聯絡詢價
查看資料表 →EP2C35F672C7N
✅ 直接替換聯絡詢價
查看資料表 →EP2C35F672C8N
✅ 直接替換聯絡詢價
查看資料表 →EP2C35F672I6N 最大額定值與電氣特性
| Series | Cyclone II |
| Logic Elements | 33,216 |
| Logic Array Blocks (LABs) | 2,100 |
| Total Memory Bits | 483,840 bits |
| Embedded 18x18 Multipliers | 150 |
| PLLs | 4 |
| Maximum User I/O Pins | 322 |
| 封裝 | 672-ball FBGA (FineLine BGA), 27 mm |
| Core Voltage | 1.15 V to 1.25 V (nominal 1.2 V) |
| I/O Supply Voltage | 3.3 V |
| 工作溫度 | -40 C to +100 C (industrial, 'I' suffix) |
| Speed Grade | 6 |
| Process Technology | 90 nm low-k dielectric |
| Logic Family | CMOS |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Lead-Free | Yes |
EP2C35F672I6N 672-ball fbga (fineline bga), 27 mm 腳位配置指南
EP2C35F672I6N（672-ball fbga (fineline bga), 27 mm 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： EP2C35F672I6N.
請參閱 資料表 以查看完整腳位配置。
典型應用
EP2C35F672I6N 適用於 6 應用s: Digital Video Processing Pipeline, Software Defined Radio (SDR) Baseband, Industrial Motor and Motion Control, ASIC Prototyping and Emulation, Embedded Vision and Machine Inspection, Low-Cost Custom Logic Integration.
Digital Video Processing Pipeline
The EP2C35F672I6N's 33,216 logic elements and 150 dedicated 18x18 multipliers make it an excellent fit for digital video processing pipelines. The 322 user I/O pins can ingest parallel video data from a camera sensor or HDMI receiver while driving an SDRAM frame buffer without external bus muxing. The 483 Kbits of embedded memory provide line buffering for deinterlacing, scaling, and color-space conversion. Placed between the video ADC and the LCD controller, the EP2C35 runs scaling and color correction in real time at 1080p60. Unlike a CPU solution, it offers deterministic latency critical for video synchronization, and unlike an ASIC it remains re-programmable for evolving codec standards.
推薦
Software Defined Radio (SDR) Baseband
The EP2C35F672I6N's 18x18 multipliers enable single-cycle multiply-accumulate operations essential for SDR baseband processing. With 150 multipliers, the device can run 150 parallel MAC operations per clock cycle, sufficient for 50-tap FIR filters, FFT butterflies, and digital down-conversion in parallel. The 4 PLLs generate the multiple sample-clock domains needed for ADC/DAC interfacing. Operating from the 1.2V core with 3.3V I/O, it bridges modern LVDS ADC outputs to legacy LVCMOS DSP back-ends. Unlike discrete DSP processors, the FPGA architecture scales parallelism directly with logic utilization, making it well-suited for multi-channel receivers.
推薦
Industrial Motor and Motion Control
The EP2C35F672I6N is well suited for industrial multi-axis motor control where deterministic loop latency and parallel PWM generation matter. Its 322 user I/O pins can drive 12+ three-phase PWM channels simultaneously while monitoring encoder feedback via LVDS inputs. The 4 PLLs generate the high-resolution PWM carrier clocks and the encoder sampling clocks from a single crystal reference. The -40C to +100C industrial temperature rating and 90nm process reliability suit factory-floor deployment. Placed between the host PLC and the IGBT gate drivers, the FPGA implements field-oriented control with sub-microsecond loop times - far faster than any MCU-based solution.
推薦
ASIC Prototyping and Emulation
The EP2C35F672I6N's 33,216 logic elements make it a useful low-cost ASIC prototyping target for designs originally targeting 60-80K gate ASICs. Designers can map the RTL into the FPGA, validate functional behavior at real-world speeds, and iterate on architecture without NRE charges. The 150 multipliers and 483 Kbits of memory support typical ASIC blocks including datapath, register file, and control logic. The JTAG interface and EPCS configuration flash enable fast turnaround. Compared to simulation, FPGA prototyping runs at MHz speeds - 1000x faster than software simulation - making system-level validation practical before committing to silicon.
推薦
Embedded Vision and Machine Inspection
The EP2C35F672I6N supports embedded vision applications requiring real-time image preprocessing before forwarding to a host processor. Its 150 18x18 multipliers accelerate convolution kernels for edge detection, thresholding, and blob analysis at full VGA-to-720p frame rates. The 483 Kbits of embedded memory hold multiple image lines and lookup tables for gamma correction. The 322 user I/O pins interface directly with parallel CMOS image sensors and drive LCD preview displays. Unlike a GPU, the FPGA provides deterministic per-frame latency, which simplifies synchronization with external triggers in factory inspection lines.
推薦
Low-Cost Custom Logic Integration
The EP2C35F672I6N can replace multiple discrete CPLDs and glue-logic ICs in cost-sensitive designs. Its 33,216 logic elements can implement bus bridges, custom peripherals, and protocol converters that would otherwise require 4-6 separate 5V CPLDs. The 322 user I/O pins handle multiple voltage domains and bus standards simultaneously - LVTTL, LVCMOS, PCI, and LVDS. The 4 PLLs eliminate external clock-generator ICs. Compared with a multi-CPLD solution, the EP2C35 reduces BOM count by 70%, PCB area by 50%, and total system cost by 30-40% in mid-volume products.
推薦
推薦產品摘要
工程參考資料，適用於 EP2C35F672I6N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP2C35F672C6N | EP2C35F672C7N | EP2C35F672C8N | EP2C35F484I6N |
|---|---|---|---|---|---|
| Package | 672-ball FBGA (27 mm) | 672-ball FBGA (same) | 672-ball FBGA (same) | 672-ball FBGA (same) | 484-ball FBGA (different) |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 33,216 | 33,216 (identical) | 33,216 (identical) | 33,216 (identical) | 33,216 (identical silicon) |
| Speed Grade | 6 | 6 (same) | 7 (slower Fmax) | 8 (fastest Fmax) | 6 (same) |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Total Memory Bits | 483,840 | 483,840 (identical) | 483,840 (identical) | 483,840 (identical) | 483,840 (identical) |
| 18x18 Multipliers | 150 | 150 (identical) | 150 (identical) | 150 (identical) | 150 (identical) |
| User I/O Pins | 322 (in 672-ball FBGA) | 322 (same package) | 322 (same package) | 322 (same package) | 322 (in 484-ball FBGA, fewer balls) |
主要差異化特點
- Industrial temperature rating at the same die (對比EP2C35F672C6N)
- Mid-tier speed grade balances performance and cost (對比EP2C35F672C8N)
- Highest I/O count in the Cyclone II family (對比EP2C35F484I6N)
設計說明
The EP2C35F672I6N requires a clean 1.2V core supply with tight regulation. A buck regulator followed by an LC filter (10uH inductor + 220uF bulk + 10uF ceramic) is recommended. Bulk-decoupling of 4x 100uF polymer or tantalum capacitors should surround the package. Place 0.1uF and 0.01uF ceramic decoupling within 5mm of every VCCINT and VCCIO pin pair. The 3.3V I/O supply has separate decoupling requirements and must be filtered from the analog PLL supplies (VCCA_PLL) with a ferrite bead.
The 672-ball FBGA package requires a minimum 4-layer PCB stack-up with continuous ground and power planes beneath the device. Use 1.0 mm ball-pitch footprint with non-solder-mask-defined (NSMD) pads for reliability. Microvia-in-pad or via-in-pad technology is recommended for inner-row balls to escape signals. Maintain at least 8 mil trace/space on outer layers and 6 mil on inner layers. A solid ground pour must cover the entire area under the BGA on layer 2 to control impedance and provide thermal dissipation.
Estimated: at 50% logic utilization and 100 MHz toggle rate, the EP2C35F672I6N dissipates approximately 1.5W-2.5W from the 1.2V core. The FBGA-672 package has a theta-JA of approximately 15 C/W with a properly designed 4-layer PCB. Junction temperature at 70C ambient stays below 110C - within the industrial limit. For high-utilization DSP designs at 200 MHz, dissipation may reach 4-6W; in this case, attach a small heatsink or use thermal vias to inner copper planes.
Do not leave any I/O bank supply (VCCIO) floating - every bank used must have its VCCIO pin connected, even if the bank is unused, to prevent latch-up. The JTAG TCK signal must be pulled to ground through a 1k-10k resistor to keep the device out of boundary-scan mode at power-up. Configuration mode pins MSEL[2:0] must be tied correctly via 1k resistors to select AS, PS, or JTAG mode - incorrect values prevent configuration.
LVDS pairs on the EP2C35F672I6N must use the dedicated true/complement pins in the same I/O bank - swapping polarity in software does not work. Route LVDS pairs with 100-ohm differential impedance, matched length within 150 mil, and continuous ground reference. Place the 100-ohm termination resistor within 200 mil of the receiver pin. The 4 PLLs require clean analog supplies (VCCA_PLL) decoupled with 10uF tantalum and 0.1uF ceramic directly at the PLL pin.
合規資訊
RoHS and lead-free compliant per Altera/Intel product documentation. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. Halogen-free status not explicitly stated in available data.
