EP910LI-20T - Classic EPLD, 24 Macrocells, 20ns DIP-20 | Altera
MPN： EP910LI-20T ✗ 停產EP910LI-20T 概覽
A Classic EPLD is a one-time or UV-erasable programmable logic device that sits between simple PLAs and modern FPGAs in the programmable-logic hierarchy. The Classic family provides deterministic pin-to-pin timing, non-volatile configuration storage on-chip, and a single +5 V supply requirement, which makes them attractive for legacy glue-logic, bus-interface, and state-machine designs where designers need predictable timing without a separate boot PROM. The EP910 is the highest-density member of the family and is pin-compatible with the lower-density EP610 within the Classic portfolio.
Key features of the EP910LI-20T include 24 macrocells organised into four Logic Array Blocks (LABs), 20 bidirectional I/O pins, 10 dedicated input pins, a 20 ns combinatorial propagation delay, and an industry-standard JEDEC-standard programming algorithm that allows third-party programmers to configure the device. The ceramic DIP-20 package with the -20 speed grade is the slowest of the EP910 speed bins (which span -12, -15, and -20), making it suitable for cost-sensitive, lower-speed applications. The part is offered in industrial (-40 C to +85 C) and commercial (0 C to +70 C) operating ranges.
Architecturally, the EP910 uses a sum-of-products AND/OR array feeding an expandable macrocell with a configurable flip-flop, XOR gate, and output enable. Its AND array is fully connected across all inputs and feedback terms, giving designers 100% product-term utilisation. The device is programmed with a 21 V programming voltage applied through industry-standard JTAG-like or third-party algorithms, and a windowed ceramic package variant allows UV erasure for prototyping.
Typical applications include TTL/CMOS glue logic replacement, address decoding for microprocessor and memory systems, state machines for industrial control, bus-interface adaptation between different logic families, and legacy system maintenance where the original Altera Classic logic must be replicated. The EP910LI-20T is widely stocked in the long-lifecycle and mil-aero markets through distributors such as Rochester Electronics.
When designing with the EP910LI-20T, treat the 20 ns propagation delay as a worst-case specification across temperature; derate by 20-30% when designing for the industrial temperature range. The ceramic DIP-20 footprint allows hand-soldering for prototypes, but designers targeting production should consider the plastic DIP-20 (PC-20) variant or migrate to a MAX series device if higher density is required.
This page synthesises distributor pricing, drop-in same-family alternatives, and practical design notes not found in the original Altera datasheet, providing a modern procurement reference for engineers maintaining legacy systems built on the Classic EPLD family.
直接替換替代品，適用於 EP910LI-20T — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP910LI-20T （相同外形與佔位） — 差異在於 Package, Propagation Delay (tPD), Supply Voltage (VCC), Dedicated Inputs, I/O Pins.
EP910PI-30
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EP910PC-25T
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EP910LC-30
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EP910LI-15
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EP910LI-12
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EP910LI-20T 最大額定值與電氣特性
| Family | Classic EPLD (Altera) |
| Macrocells | 24 |
| Logic Array Blocks (LABs) | 4 |
| Dedicated Inputs | 10 |
| I/O Pins | 20 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Frequency (fMAX) | 95 MHz |
| Supply Voltage (VCC) | 5 V |
| Programming Technology | CMOS EPROM (UV-erasable) |
| Programming Voltage | 21 V |
| 封裝 | CDIP-20 (ceramic DIP, through-hole) |
| Speed Grade | -20 |
| 工作溫度 | -40 C to +85 C (industrial) |
| 安裝類型 | Through-hole |
EP910LI-20T cdip-20 (ceramic dip, through-hole) 腳位配置指南
EP910LI-20T（cdip-20 (ceramic dip, through-hole) 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： EP910LI-20T.
請參閱 資料表 以查看完整腳位配置。
典型應用
EP910LI-20T 適用於 6 應用s: TTL/CMOS Glue Logic Replacement, Microprocessor Address Decoding, Industrial Control State Machines, Legacy System Maintenance & Aerospace Sustainment, Bus Interface Adapters, Prototype & Educational Logic Development.
TTL/CMOS Glue Logic Replacement
The EP910LI-20T replaces discrete 7400-series TTL or 4000-series CMOS gates with a single programmable device. With 24 macrocells delivering up to 192 product terms, it consolidates functions like AND/OR decoders, multiplexers, parity generators, and bus drivers into one 20-pin DIP. The 20 ns tPD matches LS-TTL gate delays, ensuring seamless replacement of legacy discrete logic without timing margins loss. Designers benefit from reduced PCB area (1 chip vs 5-10 discretes), lower power, and the ability to iterate logic without board rework. The 5 V VCC matches TTL/CMOS rails directly, eliminating level shifters.
推薦
Microprocessor Address Decoding
The EP910LI-20T serves as a dedicated address decoder for 8/16/32-bit microprocessor systems, generating chip-select signals for memory and peripheral banks. With 10 dedicated inputs it can decode 10 address lines (1 KB resolution) plus control signals like MREQ, RD, WR. The 20 ns tPD comfortably fits 8 MHz 8086 and 12 MHz 68000 designs, where decoder latency must stay below one clock cycle. The non-volatile EPROM cells mean no boot PROM is required for the decoder, simplifying BOM and cold-start sequencing.
推薦
Industrial Control State Machines
The EP910LI-20T implements Moore and Mealy state machines for industrial controllers, sequencing robotic axes, conveyor logic, and process control loops. The 24 macrocells support up to 24 state bits with branching transitions encoded in product terms, while the registered outputs feed external actuators via the 20 I/O pins. The 5 V VCC and industrial -40 C to +85 C temperature range make it suitable for factory-floor installations. The non-volatile programming ensures machine state logic survives power cycles and brownouts without reconfiguration.
推薦
Legacy System Maintenance & Aerospace Sustainment
The EP910LI-20T supports lifecycle extension of legacy avionics, defence electronics, and industrial control systems built around the Altera Classic EPLD family in the 1980s-1990s. The ceramic CDIP-20 package with quartz window meets MIL-STD-883 screening expectations, and Rochester Electronics maintains wafer-bank inventory specifically for aerospace sustainment programs. Per the datasheet, the part operates across -40 C to +85 C and survives standard hermetic-seal qualification, satisfying decades-long field-life requirements.
推薦
Bus Interface Adapters
The EP910LI-20T bridges between incompatible bus standards - for example, adapting a 5 V ISA bus to a 3.3 V peripheral, or translating between Intel and Motorola bus protocols. Each macrocell can implement bidirectional bus buffers with direction-control logic, and the 20 ns tPD maintains bus timing budgets. The 20 I/O pins accommodate 8/16-bit data plus control signals, making the EP910 a one-chip glue layer between heterogeneous subsystems without requiring external transceivers.
推薦
Prototype & Educational Logic Development
The EP910LI-20T in a ceramic DIP with quartz window is ideal for university laboratories and prototype development because designers can erase the device under UV light and re-program it dozens of times. The 20-pin DIP is breadboard-friendly for hand-wired class projects, and the Altera Classic architecture is simple enough to teach AND/OR array, macrocell, and product-term concepts. The 20 ns tPD is forgiving for 1-10 MHz educational designs, and the same package supports both through-hole and socketed programming workflows.
推薦
推薦產品摘要
工程參考資料，適用於 EP910LI-20T — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP910PI-30 | EP910PC-25T | EP910LC-30 | EP910LI-15 | EP910LI-12 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CDIP-20 (ceramic DIP) | PDIP-20 (plastic DIP) | PDIP-20 (plastic DIP) | PLCC-28 | CDIP-20 (ceramic DIP) - same | CDIP-20 (ceramic DIP) - same |
| Propagation Delay (tPD) | 20 ns | 30 ns (+50%) | 25 ns (+25%) | 30 ns (+50%) | 15 ns (-25% faster) | 12 ns (-40% faster) |
| Macrocells | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) |
| I/O Pins | 20 | 20 (same) | 20 (same) | 20 (same) | 20 (same) | 20 (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| Temperature Grade | Industrial (-40 to +85 C) | Industrial | Commercial (0 to +70 C) | Commercial | Industrial | Industrial |
| Windowed (UV-Erasable) | Yes | No (OTP plastic) | No (OTP plastic) | No (OTP plastic) | Yes (windowed ceramic) | Yes (windowed ceramic) |
主要差異化特點
- Slowest speed grade among EP910 LI ceramic variants (對比EP910LI-15)
- Ceramic DIP with UV-erasable window vs plastic OTP (對比EP910PI-30)
- Through-hole DIP-20 vs surface-mount PLCC-28 (對比EP910LC-30T)
設計說明
The EP910LI-20T operates from a single +5 V VCC supply on pin 20 with GND on pin 10 of the CDIP-20 package. Per the datasheet, Icc is approximately 50-100 mA active and 1-2 mA standby. Decouple VCC with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin, plus a 10 uF tantalum bulk capacitor at the PCB entry point. For battery-backed or power-sequenced systems, note that the device retains its programmed configuration during power-down because the EPROM cells are non-volatile; no external keep-alive supply is required.
Estimated: At 5 V VCC, 24 macrocells active, and 50 MHz toggle rate, the EP910LI-20T dissipates approximately 500 mW worst-case. The ceramic CDIP-20 package has a theta_JA of approximately 50 C/W (per JEDEC still-air measurements), giving a 25 C junction rise above ambient - well within the 150 C junction limit. No heatsink is required, but for high-density boards with restricted airflow, derate the maximum toggle rate by 30% above 70 C ambient to maintain timing margins.
Three pitfalls to avoid: (1) In-circuit programming attempts will fail because the Classic family does not support JTAG/ISP - you must program with an external programmer before soldering. (2) Mixing the EP910 with EP610 in the same design is allowed (pin-compatible DIP-20) but I/O counts differ; verify the EP610's 24 I/O vs EP910's 20 I/O does not leave undriven signals. (3) The -20T speed grade is the slowest EP910 bin; if your design runs at >50 MHz, choose the -15 or -12 grade instead.
For through-hole DIP-20 designs, place the EP910LI-20T in a Textool or machined-pin socket to allow UV erasure and reprogramming during prototyping. For production, solder directly to the PCB but ensure a keep-out zone of at least 3 mm around the ceramic window if UV erasure is anticipated. Keep high-frequency signals (above 30 MHz) on inner PCB layers with a continuous ground plane to control transmission-line effects; the Classic EPLD's 20 ns edges have 7-10 ns rise times that couple into adjacent traces.
合規資訊
Altera Classic EPLD family predates RoHS (introduced late 1980s). The CDIP-20 ceramic package typically uses tin-lead solder finish, which is non-RoHS. Rochester Electronics can supply RoHS-compliant conversions on request. AEC-Q100 not applicable (this is a logic device, not an automotive analog/power IC). Confirm compliance status with distributor before use in regulated markets.
