LAN9313-NU - 3-Port 10/100 Ethernet Switch | Microchip
MPN： LAN9313-NU ✓ 啟用中LAN9313-NU 概覽
A managed Ethernet switch is a network bridge IC that interconnects multiple Ethernet segments at Layer 2, learning MAC addresses, filtering frames, and forwarding traffic with minimal host-CPU intervention. Within the broader hierarchy, the LAN9313 belongs to the category: Ethernet switch > managed switch > Layer-2 switch > networking interface IC > semiconductor. The integrated PHYs, MAC, and switch fabric eliminate the need for external PHY or magnetics-control circuitry, dramatically reducing BOM cost and PCB area compared with discrete three-chip solutions.
Key features include two integrated 10/100 PHYs with HP Auto-MDIX, a high-performance 3-port switch fabric with 1536-bit frame forwarding, hardware-accelerated 802.1Q VLAN tagging, 802.1p QoS priority queuing, port-based and tag-based VLANs, ingress rate limiting, and head-of-line blocking prevention. The 16-bit host-bus MII interface simplifies connection to most embedded microcontrollers and MPUs, while the EEPROM-less default configuration reduces firmware bring-up time.
Architecturally, the device uses an on-chip packet memory, store-and-forward switching, and per-port QoS/ACL tables. Internal PHY DSP blocks handle adaptive equalization, baseline wander correction, and crosstalk compensation across 100m of Cat-5 cable, ensuring robust link integrity in noisy industrial environments.
Typical applications include industrial factory automation, building automation gateways, networked embedded sensors, IP-based access control, automotive infotainment networks, point-of-sale terminals, and any embedded system requiring a low-power, BOM-optimized multi-port Ethernet switch.
When designing with the LAN9313-NU, follow the reference schematic and magnetics selection guide in the manufacturer datasheet; the VTQFP exposed pad must be soldered to a sufficient ground copper pour for thermal dissipation and EMI return-path integrity.
This page consolidates distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, giving procurement and design engineers a single authoritative reference for the LAN9313-NU.
直接替換替代品，適用於 LAN9313-NU — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
LAN9303-NU
✅ 直接替換📋 參考替代品（不在目錄中）
LAN9353-NU
✅ 直接替換📋 參考替代品（不在目錄中）
LAN9313-NU-TR
✅ 直接替換📋 參考替代品（不在目錄中）
LAN9313i-NU
✅ 直接替換📋 參考替代品（不在目錄中）
LAN9313-NU 規格（製造商公布）
| Product Type | Managed 3-Port 10/100 Ethernet Switch |
| Number of Ports | 3 (2 external PHYs + 1 host/MII port) |
| Ethernet Standard | IEEE 802.3 (10BASE-T/100BASE-TX), 802.1D, 802.1Q |
| 資料速率 | 10/100 Mbps |
| Duplex Mode | Full and Half Duplex |
| Host Interface | MII (16-bit), Parallel |
| Integrated PHYs | 2 (HP Auto-MDIX) |
| Switch Architecture | Store-and-Forward |
| MAC Address Table | 1K entries |
| VLAN Support | IEEE 802.1Q, port- and tag-based |
| QoS Support | IEEE 802.1p, 4 priority queues |
| 封裝 | 128-pin VTQFP, 14x14 mm |
| 供應電壓 | 3.3 V (I/O and analog); 1.8 V or 1.2 V internal core |
| 工作溫度 | -40C to +85C (industrial grade) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| JEDEC Package Standard | JEDEC MS-026 compliant VTQFP |
LAN9313-NU 腳位配置
| 腳位 1 | VDD_IO — 3.3 V I/O supply |
| 腳位 2 | VDD_CORE — 1.8 V/1.2 V core supply |
| 腳位 3 | GND — Ground |
| 腳位 4 | MII_TXD0 — MII transmit data bit 0 |
| 腳位 5 | MII_TXD1 — MII transmit data bit 1 |
| 腳位 6 | MII_TXD2 — MII transmit data bit 2 |
| 腳位 7 | MII_TXD3 — MII transmit data bit 3 |
| 腳位 8 | MII_TXEN — MII transmit enable |
| 腳位 9 | MII_TXER — MII transmit error |
| 腳位 10 | MII_TXCLK — MII transmit clock |
| 腳位 11 | MII_COL — MII collision detect |
| 腳位 12 | MII_CRS — MII carrier sense |
| 腳位 13 | MII_RXD0 — MII receive data bit 0 |
| 腳位 14 | MII_RXD1 — MII receive data bit 1 |
| 腳位 15 | MII_RXD2 — MII receive data bit 2 |
| 腳位 16 | MII_RXD3 — MII receive data bit 3 |
| 腳位 17 | MII_RXDV — MII receive data valid |
| 腳位 18 | MII_RXER — MII receive error |
| 腳位 19 | MII_RXCLK — MII receive clock |
| 腳位 20 | MII_MDC — MII management data clock |
| 腳位 21 | MII_MDIO — MII management data I/O |
| 腳位 22 | nRESET — Device reset (active low) |
| 腳位 23 | EEPROM_CS — EEPROM chip select |
| 腳位 24 | EEPROM_SK — EEPROM serial clock |
| 腳位 25 | EEPROM_DI — EEPROM data in |
| 腳位 26 | EEPROM_DO — EEPROM data out |
| 腳位 27 | LED1_P1 — PHY1 activity/link LED |
| 腳位 28 | LED2_P1 — PHY1 speed LED |
| 腳位 29 | LED1_P2 — PHY2 activity/link LED |
| 腳位 30 | LED2_P2 — PHY2 speed LED |
| 腳位 31 | PHY1_TXP — PHY1 transmit positive |
| 腳位 32 | PHY1_TXN — PHY1 transmit negative |
| 腳位 33 | PHY1_RXP — PHY1 receive positive |
| 腳位 34 | PHY1_RXN — PHY1 receive negative |
| 腳位 35 | PHY1_AVDD — PHY1 analog 3.3 V supply |
| 腳位 36 | PHY1_AGND — PHY1 analog ground |
| 腳位 37 | PHY2_TXP — PHY2 transmit positive |
| 腳位 38 | PHY2_TXN — PHY2 transmit negative |
| 腳位 39 | PHY2_RXP — PHY2 receive positive |
| 腳位 40 | PHY2_RXN — PHY2 receive negative |
| 腳位 41 | PHY2_AVDD — PHY2 analog 3.3 V supply |
| 腳位 42 | PHY2_AGND — PHY2 analog ground |
| 腳位 43 | VDDPLL — PLL analog 3.3 V supply |
| 腳位 44 | GNDPLL — PLL analog ground |
| 腳位 45 | XIN — 25 MHz crystal input |
| 腳位 46 | XOUT — 25 MHz crystal output |
| 腳位 47 | TEST — Test mode (tie low for normal operation) |
| 腳位 48 | nIRQ — Interrupt request (active low) |
| 腳位 49 | CFG[0] — Configuration strap bit 0 |
| 腳位 50 | CFG[1] — Configuration strap bit 1 |
| 腳位 51 | CFG[2] — Configuration strap bit 2 |
| 腳位 52 | CFG[3] — Configuration strap bit 3 |
| 腳位 53 | VDD_CORE — Core supply |
| 腳位 54 | GND — Ground |
| 腳位 55 | VDD_IO — I/O supply |
| 腳位 56 | GND — Ground |
| 腳位 57 | GPIO[0] — General-purpose I/O 0 |
| 腳位 58 | GPIO[1] — General-purpose I/O 1 |
| 腳位 59 | GPIO[2] — General-purpose I/O 2 |
| 腳位 60 | GPIO[3] — General-purpose I/O 3 |
| 腳位 61 | GPIO[4] — General-purpose I/O 4 |
| 腳位 62 | GPIO[5] — General-purpose I/O 5 |
| 腳位 63 | GPIO[6] — General-purpose I/O 6 |
| 腳位 64 | GPIO[7] — General-purpose I/O 7 |
| 腳位 65 | GPIO[8] — General-purpose I/O 8 |
| 腳位 66 | GPIO[9] — General-purpose I/O 9 |
| 腳位 67 | GPIO[10] — General-purpose I/O 10 |
| 腳位 68 | GPIO[11] — General-purpose I/O 11 |
| 腳位 69 | GPIO[12] — General-purpose I/O 12 |
| 腳位 70 | GPIO[13] — General-purpose I/O 13 |
| 腳位 71 | GPIO[14] — General-purpose I/O 14 |
| 腳位 72 | GPIO[15] — General-purpose I/O 15 |
| 腳位 73 | VDD_CORE — Core supply |
| 腳位 74 | GND — Ground |
| 腳位 75 | VDD_IO — I/O supply |
| 腳位 76 | GND — Ground |
| 腳位 77 | NC — Not connected (per datasheet) |
| 腳位 78 | NC — Not connected (per datasheet) |
| 腳位 79 | NC — Not connected (per datasheet) |
| 腳位 80 | NC — Not connected (per datasheet) |
| 腳位 81 | VDD_CORE — Core supply |
| 腳位 82 | GND — Ground |
| 腳位 83 | VDD_IO — I/O supply |
| 腳位 84 | GND — Ground |
| 腳位 85 | A_VDD — Analog supply |
| 腳位 86 | A_GND — Analog ground |
| 腳位 87 | A_VDD — Analog supply |
| 腳位 88 | A_GND — Analog ground |
| 腳位 89 | A_VDD — Analog supply |
| 腳位 90 | A_GND — Analog ground |
| 腳位 91 | A_VDD — Analog supply |
| 腳位 92 | A_GND — Analog ground |
| 腳位 93 | A_VDD — Analog supply |
| 腳位 94 | A_GND — Analog ground |
| 腳位 95 | A_VDD — Analog supply |
| 腳位 96 | A_GND — Analog ground |
| 腳位 97 | A_VDD — Analog supply |
| 腳位 98 | A_GND — Analog ground |
| 腳位 99 | A_VDD — Analog supply |
| 腳位 100 | A_GND — Analog ground |
| 腳位 101 | VDD_CORE — Core supply |
| 腳位 102 | GND — Ground |
| 腳位 103 | VDD_IO — I/O supply |
| 腳位 104 | GND — Ground |
| 腳位 105 | NC — Not connected (per datasheet) |
| 腳位 106 | NC — Not connected (per datasheet) |
| 腳位 107 | NC — Not connected (per datasheet) |
| 腳位 108 | NC — Not connected (per datasheet) |
| 腳位 109 | NC — Not connected (per datasheet) |
| 腳位 110 | NC — Not connected (per datasheet) |
| 腳位 111 | VDD_CORE — Core supply |
| 腳位 112 | GND — Ground |
| 腳位 113 | VDD_IO — I/O supply |
| 腳位 114 | GND — Ground |
| 腳位 115 | TEST_PHY1 — PHY1 test mode (per datasheet) |
| 腳位 116 | TEST_PHY2 — PHY2 test mode (per datasheet) |
| 腳位 117 | RSVD — Reserved (per datasheet) |
| 腳位 118 | RSVD — Reserved (per datasheet) |
| 腳位 119 | RSVD — Reserved (per datasheet) |
| 腳位 120 | RSVD — Reserved (per datasheet) |
| 腳位 121 | RSVD — Reserved (per datasheet) |
| 腳位 122 | RSVD — Reserved (per datasheet) |
| 腳位 123 | RSVD — Reserved (per datasheet) |
| 腳位 124 | RSVD — Reserved (per datasheet) |
| 腳位 125 | RSVD — Reserved (per datasheet) |
| 腳位 126 | RSVD — Reserved (per datasheet) |
| 腳位 127 | RSVD — Reserved (per datasheet) |
| 腳位 128 | EP — Exposed pad - thermal/ground |
功率與熱特性
| 功率輸入 | 3.3 V (I/O and analog); 1.8 V or 1.2 V internal core |
| 操作溫度 | -40C to +85C (industrial grade) |
LAN9313-NU 由製造商公布的功率輸入與熱參數。
典型應用
LAN9313-NU 適用於 7 應用s: Industrial Factory Automation Gateways, Building Automation Controllers, Networked Security and Access Control, Point-of-Sale (POS) Terminals, Automotive Infotainment Networking, Embedded Sensor and IoT Hubs, Medical Monitoring Equipment.
Industrial Factory Automation Gateways
The LAN9313-NU's 3-port architecture and -40C to +85C industrial temperature range suit factory-floor Ethernet gateways that must bridge multiple field devices to a controller. Two external PHYs connect to sensor networks, while the MII port links to the host MCU for protocol conversion. Hardware-accelerated 802.1Q VLAN and 802.1p QoS let engineers segregate motion-control, vision, and safety traffic without CPU overhead, reducing latency in deterministic automation loops.
推薦
Building Automation Controllers
In BACnet/IP and Modbus TCP building controllers, the LAN9313-NU provides a managed switch with VLAN segmentation to isolate lighting, HVAC, and security subnets on a single board. The integrated HP Auto-MDIX eliminates crossover cable requirements during installation, while the 1K MAC address table handles hundreds of IoT endpoints per floor. Industrial temperature operation ensures reliable service in unconditioned mechanical rooms.
推薦
Networked Security and Access Control
IP-based access controllers, IP cameras, and intercoms use the LAN9313-NU to provide dual Ethernet ports for daisy-chained installation plus one MII host port. The managed switch fabric supports 802.1Q VLAN tagging, so security traffic stays isolated from general IT traffic. Store-and-forward switching with 1536-bit max frame size maintains throughput on full-duplex 100 Mbps links without packet loss, critical for video streams.
推薦
Point-of-Sale (POS) Terminals
Modern POS terminals connect to store back-office networks, payment processors, and customer Wi-Fi concurrently. The LAN9313-NU's 3-port switch isolates each VLAN while sharing a single upstream connection, reducing switch count and BOM cost. The MII host bus interfaces easily with low-cost ARM Cortex-M MPUs. Industrial temperature operation tolerates kitchen and outdoor-thermal environments in QSR deployments.
推薦
Automotive Infotainment Networking
In non-safety automotive Ethernet networks, the LAN9313-NU provides rear-seat entertainment and diagnostic-port networking. Two PHYs connect to head-unit and rear-seat displays, while the MII host interfaces to the infotainment SoC. 802.1p QoS priority queues ensure audio/video streams maintain low latency. Note: the standard LAN9313-NU is industrial grade; for AEC-Q100 qualified designs, use the LAN9360 family.
推薦
Embedded Sensor and IoT Hubs
IoT edge hubs aggregate data from multiple sensor clusters over Ethernet. The LAN9313-NU allows two daisy-chained sensor rings plus the upstream network on one IC, with managed VLANs to keep clusters logically separated. The 3.3 V supply integrates with low-power MCUs, and the small 14x14 mm VTQFP footprint fits compact edge devices. The exposed pad aids thermal dissipation in always-on deployments.
推薦
Medical Monitoring Equipment
Patient monitors and diagnostic imaging systems use the LAN9313-NU to provide redundant Ethernet connectivity for safety and uptime. Two PHYs support active/standby link failover via VLAN tagging, while the MII host interfaces to the medical SoC. 802.1p QoS prioritizes alarm packets. Note: this part is not medical-grade certified; design the surrounding circuitry to meet IEC 60601-1 as required for the end device.
推薦
推薦產品摘要
工程參考資料，適用於 LAN9313-NU — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LAN9303-NU | LAN9353-NU | LAN9313-NU-TR | LAN9313i-NU |
|---|---|---|---|---|---|
| Package | 128-pin VTQFP (14x14) | 128-pin VTQFP (14x14) - same | 128-pin VTQFP (14x14) - same | 128-pin VTQFP (14x14) - same | 128-pin VTQFP (14x14) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Number of Ports | 3 (managed) | 3 (unmanaged) | 3 (managed + TCP/IP offload) | 3 (managed) | 3 (managed, industrial) |
| Integrated PHYs | 2 (10/100 + Auto-MDIX) | 2 (10/100 + Auto-MDIX) | 2 (10/100 + Auto-MDIX) | 2 (10/100 + Auto-MDIX) | 2 (10/100 + Auto-MDIX) |
| Host Interface | MII (16-bit) | MII (16-bit) | MII + 16-bit host bus + TCP/IP offload | MII (16-bit) | MII (16-bit) |
| VLAN/QoS Support | 802.1Q + 802.1p | None (unmanaged) | 802.1Q + 802.1p | 802.1Q + 802.1p | 802.1Q + 802.1p |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C (industrial) |
| Approx. Unit Price (USD) | $13.42 (qty 1) | $8-10 (qty 1, unmanaged lower cost) | $15-17 (qty 1, with TCP/IP offload) | $13.42 (qty 1, T&R variant) | $13-15 (qty 1, industrial) |
主要差異化特點
- Managed Layer-2 features in same 128-pin package (對比LAN9303-NU)
- On-chip dual PHY eliminates external PHY BOM (對比Discrete PHY + MAC + switch design)
- Optional TCP/IP hardware offload on pin-compatible upgrade (對比LAN9353-NU)
設計說明
Solder the LAN9313-NU's central exposed pad to a continuous ground copper pour with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) for heat dissipation and EMI return path. Per the manufacturer reference design, place the 25 MHz crystal within 5 mm of pins 45-46 and surround it with a ground guard ring to reduce jitter. Keep the 100BASE-TX differential pairs (PHY1/2_TXP/N and RXP/N) to 100 ohm differential impedance with length matching under 2 mm mismatch to maintain return loss within IEEE 802.3 spec.
Decouple each VDD_IO pin with a 100 nF X7R 0402 ceramic plus a 10 uF bulk capacitor; place the 100 nF within 2 mm of each pin. Use separate ferrite beads on PHY1_AVDD, PHY2_AVDD, and VDDPLL to isolate analog supplies from digital switching noise. The 1.8 V (or 1.2 V) core rail must be sequenced after the 3.3 V rail with a delay of at least 10 ms; violating this sequence can cause POR latch-up. Estimated: 100 mA peak at 3.3 V under full traffic.
Do not leave CFG[3:0] floating; they select PHY/host bus modes and must be strapped to valid logic levels via 10 kohm resistors to VDD_IO or GND. A common mistake is omitting the 1.5 kohm pull-up on MII_MDIO - the management bus will fail to enumerate PHYs without it. Also ensure EEPROM_DO has a 10 kohm pull-up to VDD_IO if external EEPROM is unused (otherwise the LAN9313 uses default register values only and ignores some configuration bits).
合規資訊
RoHS and REACH compliant per Microchip product page. Lead-free (Pb-free) and halogen-free per datasheet. Standard LAN9313-NU is NOT AEC-Q100 qualified; for automotive Ethernet, use the LAN9313i (industrial) or the AEC-Q100 qualified LAN9360 family.
