LTC2266IUJ-12 - 12-Bit 80Msps Dual ADC | Analog Devices
MPN： LTC2266IUJ-12 ✓ 啟用中LTC2266IUJ-12 概覽
A pipelined ADC is a high-speed analog-to-digital converter architecture that resolves one or two bits per clock stage across multiple cascaded gain stages, achieving tens to hundreds of MSps while keeping per-stage power dissipation modest. Pipelined ADCs sit in the broader hierarchy of Nyquist-rate data converters (SAR, pipeline, flash), and are widely used in communications infrastructure, digital oscilloscopes, and imaging systems where sample rate matters more than absolute DC precision. The LTC2266-12 belongs to Analog Devices' LTC2266 family of dual ADCs, which shares pinout with the 14-bit LTC2266-14 and 10-bit LTC2266-10 versions, enabling a single PCB layout to support multiple resolution points.
Key features include 64.9 dB SNR (typical), 80 dB SFDR, an internal reference, shutdown and nap power-down modes for energy-conscious designs, and a flexible LVDS or CMOS output interface selectable through the SPI port. The integrated bypass-and-decoupling network lets the part operate from a single 1.8 V analog supply, simplifying board design compared to discrete ADC plus driver arrangements.
Architecturally, each channel uses a multi-stage switched-capacitor pipeline fronted by a wideband track-and-hold, followed by digital error correction. The dual ADC architecture allows I/Q capture in direct-conversion receivers or simultaneous sampling of two sensor channels in instrumentation.
Typical applications include software-defined radio receivers, medical imaging front-ends, multi-channel data acquisition modules, communications baseband digitizers, and handheld oscilloscope or spectrum analyzer probes. When designing with this device, pay attention to LVDS/CMOS output termination and decoupling close to the supply pins; for demanding spurious performance, use the internal dither mode enabled via SPI.
直接替換替代品，適用於 LTC2266IUJ-12 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2266IUJ-12 （相同外形與佔位） — 差異在於 RoHS Status, Resolution, Analog Supply Voltage, Configuration Interface, Number of Channels.
LTC2266CUJ-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2266IUJ-12#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2266IUJ-12#TRPBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2266IUJ-14
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2265CUJ-12
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →LTC2260IUJ-12
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →LTC2259IUJ-12
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2266IUJ-12 最大額定值與電氣特性
| 解析度 | 12 bits |
| Number of Channels | 2 |
| 取樣率 | 80 MSps |
| Architecture | Pipelined |
| Input Range | 1 Vp-p to 2 Vp-p (selectable) |
| Full Power Bandwidth | 800 MHz |
| Analog Supply Voltage | 1.8 V |
| Output Interface | LVDS or CMOS (SPI-selectable) |
| 工作溫度範圍 | -40C to +85C (I grade) |
| 封裝 | 40-QFN (6 mm x 6 mm) |
| 安裝類型 | Surface Mount |
| Shutdown / Nap Modes | Yes |
| Configuration Interface | Serial SPI |
| Pin Compatibility Family | 14-bit LTC2266-14 and 10-bit LTC2266-10 (same 40-QFN) |
| RoHS 狀態 | Compliant (lead-free #PBF suffix) |
| Demo Board | DC1532A-I |
LTC2266IUJ-12 腳位配置
| 腳位 1 | GND — Ground reference |
| 腳位 2 | INA+ — Channel A positive analog input |
| 腳位 3 | INA- — Channel A negative analog input |
| 腳位 4 | VCM_A — Channel A common-mode voltage |
| 腳位 5 | VREF — Internal reference bypass |
| 腳位 6 | GND — Ground reference |
| 腳位 7 | VDD — 1.8 V analog supply |
| 腳位 8 | GND — Ground reference |
| 腳位 9 | ENC+ — Encode (clock) positive input |
| 腳位 10 | ENC- — Encode (clock) negative input |
| 腳位 11 | GND — Ground reference |
| 腳位 12 | OUTCLK+ — Output clock positive (LVDS) |
| 腳位 13 | OUTCLK- — Output clock negative (LVDS) |
| 腳位 14 | GND — Ground reference |
| 腳位 15 | D0+ — Data output 0 positive |
| 腳位 16 | D0- — Data output 0 negative |
| 腳位 17 | D1+ — Data output 1 positive |
| 腳位 18 | D1- — Data output 1 negative |
| 腳位 19 | D2+ — Data output 2 positive |
| 腳位 20 | D2- — Data output 2 negative |
| 腳位 21 | D3+ — Data output 3 positive |
| 腳位 22 | D3- — Data output 3 negative |
| 腳位 23 | D4+ — Data output 4 positive |
| 腳位 24 | D4- — Data output 4 negative |
| 腳位 25 | D5+ — Data output 5 positive |
| 腳位 26 | D5- — Data output 5 negative |
| 腳位 27 | D6+ — Data output 6 positive |
| 腳位 28 | D6- — Data output 6 negative |
| 腳位 29 | D7+ — Data output 7 positive |
| 腳位 30 | D7- — Data output 7 negative |
| 腳位 31 | D8+ — Data output 8 positive |
| 腳位 32 | D8- — Data output 8 negative |
| 腳位 33 | D9+ — Data output 9 positive |
| 腳位 34 | D9- — Data output 9 negative |
| 腳位 35 | D10+ — Data output 10 positive |
| 腳位 36 | D10- — Data output 10 negative |
| 腳位 37 | D11+ — Data output 11 positive |
| 腳位 38 | D11- — Data output 11 negative |
| 腳位 39 | SDO — SPI serial data output |
| 腳位 40 | GND — Ground reference and exposed pad |
典型應用
LTC2266IUJ-12 適用於 6 應用s: Software-Defined Radio Baseband Digitizer, Multi-Channel Data Acquisition Module, Medical Imaging Front-End, Communications Baseband Receiver, Handheld Oscilloscope or Spectrum Analyzer, Industrial Process Control and Instrumentation.
Software-Defined Radio Baseband Digitizer
The LTC2266IUJ-12's dual 80 MSps 12-bit ADC channels capture I and Q baseband signals simultaneously from a direct-conversion RF front-end. Its 800 MHz full-power bandwidth preserves signal integrity above the Nyquist zone and the LVDS output option minimizes digital switching noise coupling back into the LNA/mixer stage. For an SDR receiver targeting 30 MHz IF bandwidth, the 80 MSps sample rate provides comfortable margin for digital filtering and decimation, while the integrated dual channels halve PCB area compared to two discrete ADC solutions.
推薦
Multi-Channel Data Acquisition Module
In a multi-channel DAQ system the LTC2266IUJ-12 digitizes two analog inputs simultaneously at 80 MSps, allowing phase-coherent capture of paired sensor channels such as vibration probes or differential analog signals. The single 1.8 V analog supply reduces power-rail complexity, and shutdown/nap modes cut quiescent power when only one channel is in use. Combined with the SPI configuration port, the same PCB can host 8, 16, or more synchronized ADC channels for high-channel-count test and measurement systems.
推薦
Medical Imaging Front-End
The LTC2266IUJ-12's dual simultaneous-sampling architecture fits ultrasound beamforming front-ends, where pairs of transducer return signals must be digitized synchronously. The 12-bit resolution provides adequate grayscale depth for mid-range ultrasound systems, and the LVDS digital outputs are essential to keep switching transients away from sensitive analog preamp stages. The 1.8 V supply and small 6x6 mm QFN footprint enable compact handheld probe designs with high channel density per square centimeter.
推薦
Communications Baseband Receiver
Cellular base station and small-cell receivers use the LTC2266IUJ-12 to digitize dual-polarity antenna streams in MIMO configurations. At 80 MSps the part handles LTE, 5G NR, and Wi-Fi baseband bandwidths with margin for digital pulse shaping. The selectable 1-2 Vp-p input range accommodates different LNA output swings, while the SPI port allows in-system reconfiguration for multi-standard radios. Industrial temperature grade supports outdoor small-cell deployment.
推薦
Handheld Oscilloscope or Spectrum Analyzer
Portable oscilloscopes benefit from the LTC2266IUJ-12's dual-channel simultaneous sampling at 80 MSps, providing both channels of a two-channel scope on a single IC. The low 1.8 V supply consumption extends battery life, and the shutdown mode further reduces quiescent drain when the scope enters standby. The CMOS output mode simplifies interface to low-cost FPGAs in entry-level instruments, while LVDS serves higher-performance benchtop designs with tighter noise budgets.
推薦
Industrial Process Control and Instrumentation
The LTC2266IUJ-12's industrial -40C to +85C operating range and dual simultaneous-sampling channels suit multi-loop process control systems that digitize sensor pairs (e.g., pressure plus temperature, or strain gauge bridge plus reference). The integrated dual channels reduce BOM cost and PCB area versus two discrete ADC solutions, and the internal reference eliminates external reference drift concerns. Shutdown modes enable duty-cycled sampling in battery-powered field instrumentation.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2266IUJ-12 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2266CUJ-12 | LTC2266IUJ-14 | LTC2265CUJ-12 | LTC2259IUJ-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits |
| Sampling Rate | 80 MSps | 80 MSps | 80 MSps | 65 MSps | 80 MSps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +85C (I grade) |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Interface | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS |
主要差異化特點
- Dual simultaneous-sampling ADC channels in a single 6x6 mm QFN (對比LTC2259IUJ-12)
- Pin-compatible 12-bit and 14-bit family (對比LTC2266IUJ-14)
- Industrial temperature grade in same package as commercial grade (對比LTC2266CUJ-12)
設計說明
The 40-QFN (6x6) package has an exposed thermal pad that MUST be soldered to a continuous ground plane on the top PCB layer for both electrical performance and thermal dissipation. Use at least 4 thermal vias under the pad connecting to inner ground planes. Decouple each VDD pin with a 0.1 uF X7R ceramic capacitor placed within 3 mm of the pin; add a bulk 10 uF tantalum or ceramic capacitor near the supply entry point to handle clock-frequency current transients.
Route the LVDS output pairs (D0-D11) as 100 ohm differential transmission lines with matched lengths within each pair (skew < 50 ps). When using CMOS output mode, place series damping resistors near the ADC output pins to limit current transients. Keep digital output traces away from the analog input traces (INA, INB) by at least 3 line widths or use a guard ground trace to minimize digital-to-analog coupling.
Do not leave unused analog inputs floating - tie them to the VCM common-mode voltage via a 1 kohm resistor to prevent charge-injection kickback into active channels. Always apply the encode clock BEFORE releasing shutdown (via SPI) to avoid spurious wake-up transitions. When using the internal reference, the VREF bypass capacitor (typically 2.2 uF) is mandatory; omitting it degrades SNR by 3-5 dB. Verify SPI register defaults against the datasheet before any custom configuration.
Estimated: total quiescent power at 80 MSps with both channels active is approximately 130 mW per channel from the 1.8 V supply (from datasheet). Using the shutdown mode drops this to under 1 mW per channel, and the nap mode reduces power by ~50% when sampling below 40 MSps. Power-rail sequencing is not critical; the part tolerates simultaneous power-up of VDD and DVDD with no latch-up risk in normal operation.
合規資訊
RoHS compliant per the #PBF suffix designation on the lead-free variant. Not AEC-Q100 qualified - choose ADI's automotive-grade ADC family for vehicle applications. REACH status confirmed via Analog Devices product declaration.
