LTC2266CUJ-12 - 12-Bit 80Msps Dual ADC, 40-QFN | Analog Devices
MPN： LTC2266CUJ-12 ✓ 啟用中LTC2266CUJ-12 概覽
An ADC (analog-to-digital converter) is a data converter integrated circuit that translates continuous analog voltage levels into discrete digital codes, sitting at the boundary between the analog signal chain and the digital processing domain. Within the broader semiconductor taxonomy, the LTC2266CUJ-12 is a successive-approximation/pipelined ADC -> ADC -> data converter IC -> integrated circuit. Pipelined ADCs are the dominant architecture for sampling rates from ~10 Msps to several hundred Msps, offering the best trade-off between speed, resolution, and power dissipation for communications, imaging, and test-and-measurement front ends.
Key features of the LTC2266CUJ-12 include 12-bit resolution, 80 Msps sample rate, two matched ADC channels, 800 MHz full-power bandwidth, low power dissipation, SPI-port configurable modes, shutdown and nap power-down modes, and pin compatibility with the 14-bit LTC2266-14 and LTC2261-14 family. The dual-channel integration halves board area versus two discrete single-channel ADCs and eliminates the channel-to-channel skew inherent in time-interleaved solutions.
The pipelined architecture uses multi-bit/stage gain stages with digital error correction, delivering excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) while keeping per-channel power below 100 mW typical. Internal references and a low-jitter clock buffer reduce external component count, and the SPI port allows runtime configuration of input range, output data format, and power modes.
Typical applications include communications baseband and IF digitizers, medical imaging receivers, portable and battery-powered test equipment, multi-channel data acquisition systems, and diversity radio receivers. The dual channel also makes it well-suited to I/Q demodulation in direct-conversion receivers.
When designing with the LTC2266CUJ-12, pay attention to analog input drive network (transformer or active driver), low-jitter clock source, and decoupling at each supply pin. The exposed pad (EP) must be soldered to a continuous ground plane to meet the rated thermal performance; the SPI pins are 1.8V-3.3V logic and require level shifting on hosts that run above 3.3V.
This page synthesizes Analog Devices datasheet specifications, distributor pricing tiers, drop-in compatible alternatives, and PCB design notes not bundled in the manufacturer datasheet. All values are anchored to distributor data as of 2026-10-13.
直接替換替代品，適用於 LTC2266CUJ-12 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2266CUJ-12 （相同外形與佔位） — 差異在於 RoHS Status, Resolution, Package, Operating Temperature, Output Interface.
LTC2266IUJ-12#PBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2266CUJ-12#TRPBF
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2265CUJ-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2263CUJ-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2260CUJ-14
✅ 直接替換聯絡詢價
查看資料表 →LTC2258CUJ-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2266CUJ-12 最大額定值與電氣特性
| 解析度 | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| 取樣率 | 80 Msps |
| Architecture | Pipelined |
| Input Range | 1 Vp-p to 2 Vp-p (selectable) |
| Full-Power Input Bandwidth | 800 MHz |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| 封裝 | 40-pin QFN (6 mm x 6 mm) with exposed pad |
| 安裝類型 | Surface Mount |
| 工作溫度 | 0 C to +70 C (commercial) |
| Configuration Interface | Serial SPI port |
| Power-Saving Modes | Shutdown and Nap modes |
| Pin-Compatible Family | 14-bit LTC2266-14 and LTC2261-14 |
| RoHS 狀態 | Compliant (PBF suffix) |
| MSL 等級 | 1 (per JEDEC J-STD-020) |
LTC2266CUJ-12 腳位配置
| 腳位 1 | INA+ — Channel A positive analog input |
| 腳位 2 | INA- — Channel A negative analog input |
| 腳位 3 | GND — Analog ground reference |
| 腳位 4 | VCM — Common-mode voltage output |
| 腳位 5 | INB+ — Channel B positive analog input |
| 腳位 6 | INB- — Channel B negative analog input |
| 腳位 7 | GND — Analog ground reference |
| 腳位 8 | REF — Reference voltage pin |
| 腳位 9 | GND — Analog ground reference |
| 腳位 10 | VDD — 1.8 V analog supply |
| 腳位 11 | GND — Analog ground reference |
| 腳位 12 | ENC+ — Encode clock positive input |
| 腳位 13 | ENC- — Encode clock negative input (complementary) |
| 腳位 14 | GND — Clock ground reference |
| 腳位 15 | OVDD — 1.8 V to 3.3 V output driver supply |
| 腳位 16 | D0A — Channel A data output bit 0 (LSB) |
| 腳位 17 | D1A — Channel A data output bit 1 |
| 腳位 18 | D2A — Channel A data output bit 2 |
| 腳位 19 | D3A — Channel A data output bit 3 |
| 腳位 20 | D4A — Channel A data output bit 4 |
| 腳位 21 | D5A — Channel A data output bit 5 |
| 腳位 22 | D6A — Channel A data output bit 6 |
| 腳位 23 | D7A — Channel A data output bit 7 |
| 腳位 24 | D8A — Channel A data output bit 8 |
| 腳位 25 | D9A — Channel A data output bit 9 |
| 腳位 26 | D10A — Channel A data output bit 10 |
| 腳位 27 | D11A — Channel A data output bit 11 (MSB) |
| 腳位 28 | D0B — Channel B data output bit 0 (LSB) |
| 腳位 29 | D1B — Channel B data output bit 1 |
| 腳位 30 | D2B — Channel B data output bit 2 |
| 腳位 31 | D3B — Channel B data output bit 3 |
| 腳位 32 | D4B — Channel B data output bit 4 |
| 腳位 33 | D5B — Channel B data output bit 5 |
| 腳位 34 | D6B — Channel B data output bit 6 |
| 腳位 35 | D7B — Channel B data output bit 7 |
| 腳位 36 | D8B — Channel B data output bit 8 |
| 腳位 37 | D9B — Channel B data output bit 9 |
| 腳位 38 | D10B — Channel B data output bit 10 |
| 腳位 39 | D11B — Channel B data output bit 11 (MSB) |
| 腳位 40 | CS — SPI chip select / configuration (also serves as OF pin per family) |
| 腳位 EP | EP — Exposed pad - must be soldered to analog ground for thermal dissipation |
典型應用
LTC2266CUJ-12 適用於 6 應用s: Communications IF/Baseband Digitizer, Medical Imaging Receiver, Portable Test and Measurement, Multi-Channel Data Acquisition, Diversity Radio Receiver, Industrial Process Control.
Communications IF/Baseband Digitizer
The LTC2266CUJ-12 fits communications IF/baseband digitizers because its 12-bit resolution at 80 Msps captures 30+ MHz of signal bandwidth per channel with the 800 MHz full-power input bandwidth enabling direct IF undersampling. Dual matched channels simplify I/Q digitization in direct-conversion receivers, while the SPI port lets the baseband processor reconfigure input range at runtime. Power dissipation stays below 100 mW per channel, easing thermal design in compact radio modules.
推薦
Medical Imaging Receiver
The LTC2266CUJ-12 is suitable for medical imaging receiver front ends such as ultrasound beamformers and portable patient monitors, where its dual-channel integration reduces board area and channel-to-channel skew versus two discrete ADCs. The 12-bit resolution at 80 Msps is sufficient for mid-tier ultrasound channels, and the Nap/Shutdown modes extend battery life in portable carts. Pin compatibility with the 14-bit LTC2266-14 family provides a clear upgrade path to higher-resolution systems.
推薦
Portable Test and Measurement
The LTC2266CUJ-12 is well-matched to portable oscilloscope and spectrum analyzer front ends, where its 80 Msps sample rate and 800 MHz input bandwidth capture fast transients while keeping per-channel power low enough for handheld battery operation. The Shutdown and Nap modes can drop quiescent draw during standby, and the SPI port enables auto-ranging input stages. The 40-QFN (6x6 mm) footprint is small enough for dense multi-channel front-end cards.
推薦
Multi-Channel Data Acquisition
The LTC2266CUJ-12 fits multi-channel data acquisition systems where simultaneous sampling of two signals is required, such as vibration analysis, phase measurement, and quadrature demodulation. Two matched ADCs sharing a single clock eliminate inter-channel skew, and the 12-bit resolution is sufficient for many industrial control loops. The 40-QFN package supports dense PCB layouts and exposes a ground pad for thermal management.
推薦
Diversity Radio Receiver
The LTC2266CUJ-12 is ideal for diversity radio receiver chains, where two matched ADCs simultaneously digitize the main and antenna-diversity paths for maximum-ratio combining in the baseband processor. The 800 MHz full-power input bandwidth permits direct digitization of L-band or S-band IFs, eliminating a down-conversion stage. The 12-bit resolution at 80 Msps comfortably captures the channel bandwidth for Wi-Fi, LTE, and proprietary narrowband protocols.
推薦
Industrial Process Control
The LTC2266CUJ-12 (and its industrial-grade LTC2266IUJ-12 sibling) is suited to industrial process control loops requiring simultaneous sampling of two sensor channels, such as pressure transducers, strain gauges, and three-phase current monitors. Pin compatibility with the 14-bit LTC2266-14 family provides a roadmap to higher precision without PCB redesign. The 40-QFN (6x6 mm) package and 1.8 V supply simplify integration into 3.3 V and 5 V mixed-voltage systems with level shifters.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2266CUJ-12 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2266IUJ-12#PBF | LTC2266CUJ-12#TRPBF | LTC2265CUJ-12 | LTC2263CUJ-12 | LTC2260CUJ-14 |
|---|---|---|---|---|---|---|
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same family |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit | 12 bit |
| Sample Rate | 80 Msps | 80 Msps | 65 Msps | 25 Msps | 105 Msps | 65 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 2 |
| Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 750 MHz |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Supply Voltage | 1.8 V analog, 1.8 V digital, 1.8-3.3 V OVDD | 1.8 V / 1.8-3.3 V | 1.8 V / 1.8-3.3 V | 1.8 V / 1.8-3.3 V | 1.8 V / 1.8-3.3 V | 1.8 V / 1.8-3.3 V |
主要差異化特點
- Dual matched channels on a single chip (對比LTC2260CUJ-14)
- Industrial-temp drop-in option (對比LTC2265CUJ-12)
- Wide 800 MHz analog input bandwidth (對比LTC2263CUJ-12)
設計說明
Solder the exposed pad (EP) of the 40-QFN package to a continuous analog ground plane using an array of thermal vias to meet rated thermal performance. Place input capacitors, common-mode bypass, and reference decoupling within 2-3 mm of the respective pins, and split analog and digital ground planes only at the EP under the device. This minimizes return-path inductance and preserves SNR/SFDR at 80 Msps.
Drive the ENC+/ENC- differential encode clock from a low-jitter clock source (jitter < 200 fs rms); signal-to-noise ratio at 80 Msps is highly sensitive to sample-clock jitter. Use a clock buffer/transformer (e.g., ETC1-1-13) if a single-ended CMOS clock must be converted to differential. Skew between ENC+ and ENC- directly translates to aperture error in the on-chip S/H, so route them as a length-matched pair.
Use separate LDOs (e.g., LT3042, LT3010) for the 1.8 V analog (VDD) and digital (OVDD) rails, with pi-filter networks to isolate switching noise from sensitive analog circuitry. Decouple each VDD pin with a 10 uF ceramic + 0.1 uF X7R in parallel, placed within 1 mm of the pin. The shutdown mode drops quiescent current to microampere levels - assert it when the host is not actively sampling.
合規資訊
RoHS compliance confirmed by the #PBF suffix per Analog Devices / Linear Technology product marking. The 'C' in LTC2266CUJ-12 denotes the commercial 0C to +70C temperature grade; the IUJ-12 variant is industrial. No AEC-Q100 grade is offered for this family.
