TDA235E5 - 2A/mm² Dual-Phase Smart Power Stage | Infineon
MPN： TDA235E5 ✓ 啟用中TDA235E5 概覽
A smart power stage is a fully integrated point-of-load (POL) building block that contains the high-side and low-side MOSFETs, the gate driver, current sensing, and protection in one package. Smart power stages sit inside the broader power management hierarchy: voltage regulator module (VRM) -> multiphase buck controller -> smart power stage -> POL conversion for CPUs, GPUs, and AI ASICs. By integrating driver and FETs, the smart power stage minimizes dead time, switching losses, and parasitic loop inductance, enabling higher switching frequency and tighter regulation.
Key features include 2 A/mm² power density, 300 A peak current per stage, dual-phase architecture for multiphase VR topologies, integrated current-temperature telemetry for control ICs, and liquid cooling support. The 6 x 6 x 0.8 mm³ package enables placement directly under the AI accelerator cold plate, supporting vertical power delivery (VPD) architectures that reduce PCB current path length by an order of magnitude compared to lateral delivery.
Typical applications include AI accelerator core rails (HBM, GPU, ASIC), hyperscale data center vertical power delivery, 48 V to point-of-load conversion stages, server CPU/GPU multiphase VRs, and high-performance computing (HPC) POLs. The TDA235E5 also supports liquid-cooled cold-plate designs common in next-generation AI server racks.
When designing with TDA235E5, ensure the multiphase PWM controller is Infineon-compatible (OptiMOS family), follow the PCB layout guideline for thermal pad connection to inner copper layers, and verify current sharing accuracy between the two integrated phases. The integrated current telemetry outputs must be routed to the controller's IMON input with minimal noise pickup.
This page synthesizes Infineon press release specifications, distributor stock information, and practical VR design notes not collated in the original press brief.
直接替換替代品，適用於 TDA235E5 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： TDA235E5 （相同外形與佔位） — 差異在於 Mounting Type, Package, Power Density, Telemetry.
TDA235E0
✅ 直接替換聯絡詢價
查看資料表 →TDA21472
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
TDA21536
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ISL99227
✅ 直接替換📋 參考替代品（不在目錄中）
MP8795
✅ 直接替換📋 參考替代品（不在目錄中）
TDA235E5 最大額定值與電氣特性
| Product Type | Dual-phase smart power stage |
| Architecture | Dual-phase, integrated gate driver + OptiMOS 6 MOSFETs |
| Power Density | >2 A/mm² |
| Peak Current per Stage | 300 A |
| 封裝 | PG-MLGA-40 (6 x 6 x 0.8 mm³) |
| 腳位數 | 40 |
| Integrated MOSFET Technology | OptiMOS 6 |
| Cooling Support | Liquid cooling and forced air |
| Telemetry | Integrated current and temperature reporting |
| Target Topology | Multiphase buck, vertical power delivery (VPD) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Lead-Free | Yes |
| Compatible Controller Family | Infineon digital multiphase PWM controllers |
TDA235E5 pg-mlga-40 (6 x 6 x 0.8 mm³) 腳位配置指南
TDA235E5（pg-mlga-40 (6 x 6 x 0.8 mm³) 封裝）的腳位配置。 此功率元件具有閘極、汲極與源極端子。對於非極性封裝，請參閱製造商資料表以取得確切的第 1 腳方向與佈局詳細資訊。常見應用包括電源設計、馬達驅動與負載切換。
無詳細腳位定義資料： TDA235E5.
請參閱 資料表 以查看完整腳位配置。
典型應用
TDA235E5 適用於 6 應用s: AI Accelerator Core Rail VR, Hyperscale Data Center Vertical Power Delivery, 48V to Point-of-Load Conversion Stage, Server CPU/GPU Multiphase VR, High-Performance Computing (HPC) POL, Liquid-Cooled AI Accelerator Cold Plate.
AI Accelerator Core Rail VR
The TDA235E5 directly powers AI GPU/ASIC core rails requiring 200-300 A peak transients during training workloads. Its 2 A/mm² power density and dual-phase architecture let one device replace four conventional discrete phases, halving PCB area on the accelerator cold-plate side. The integrated OptiMOS 6 stage achieves sub-1 mΩ loop inductance between driver and FET, eliminating the switching spike overshoot that limits discrete designs above 1 MHz. Combined with the PG-MLGA-40 6 x 6 x 0.8 mm³ footprint that mounts directly under the cold plate, TDA235E5 enables vertical power delivery (VPD) topologies that shorten the current path by ~10x compared to lateral delivery. Liquid cooling support is built in.
推薦
Hyperscale Data Center Vertical Power Delivery
The TDA235E5's PG-MLGA-40 6 x 6 x 0.8 mm³ footprint is engineered for vertical power delivery (VPD) where power stages mount directly beneath the processor package, eliminating the lateral PCB current path that dominates loss in conventional server VRs. With 2 A/mm² power density and 300 A peak current, the TDA235E5 supports 48 V-to-POL intermediate bus architectures powering hyperscale AI training clusters. The integrated current and temperature telemetry feed back to the multiphase PWM controller for adaptive voltage positioning, optimizing efficiency across the full load range of GPU/HBM transients. Liquid-cooling compatibility means stages can be co-mounted on the same cold plate as the AI ASIC.
推薦
48V to Point-of-Load Conversion Stage
In 48 V server architectures the TDA235E5 sits on the secondary side of an isolated bus converter, delivering the final 0.8 V to 1.8 V core voltage to AI ASICs at 200-300 A. The 300 A peak current capability per stage lets designers use fewer stages for a given load, cutting BOM cost and PCB area compared to discrete designs that would need 8-12 conventional phases. The integrated OptiMOS 6 stage achieves switching frequencies above 1 MHz with minimal dead time, enabling smaller output inductors and capacitors on the POL side. The integrated temperature monitor reports junction telemetry to the system controller for thermal throttling decisions critical in rack-scale AI deployments.
推薦
Server CPU/GPU Multiphase VR
For conventional lateral VR topologies in 1U/2U servers, the TDA235E5 provides the high-current phase building block for multiphase buck converters powering server CPUs and GPUs. A typical 6-phase VR using TDA235E5 stages can deliver 1.8 kA peak, sufficient for 350 W TDP server CPUs and mainstream data-center GPUs. The integrated current telemetry eliminates external current-sense resistors and amplifiers, reducing BOM count and PCB area on the VR section. The PG-MLGA-40 footprint allows direct top-side heatsink attachment for rack designs that still use forced-air cooling.
推薦
High-Performance Computing (HPC) POL
HPC systems based on FPGAs, custom ASICs, or high-core-count CPUs benefit from the TDA235E5's combination of high current density and integrated telemetry. The 2 A/mm² power density allows denser POL designs around HPC processors where board area is at a premium. Integrated OptiMOS 6 devices with optimized driver-FET matching deliver higher efficiency than discrete solutions, reducing cooling requirements in dense HPC racks. The current and temperature reporting enable adaptive voltage scaling and per-phase current balancing through the multiphase controller, critical for transient-heavy HPC workloads.
推薦
Liquid-Cooled AI Accelerator Cold Plate
The TDA235E5 is explicitly designed for liquid-cooled AI server racks where power stages share the cold plate with the AI ASIC itself. With PG-MLGA-40 6 x 6 x 0.8 mm³ dimensions and a thermal pad optimized for top-side cold-plate mounting, the TDA235E5 can be co-located with the GPU/HBM stack. The 2 A/mm² power density and 300 A peak current support the transient demands of training workloads that would overheat conventional discrete stages. Cold-plate cooling removes the limit on power-stage power dissipation, enabling the 300 A peak current rating to be sustained for longer thermal envelopes than air-cooled designs.
推薦
推薦產品摘要
工程參考資料，適用於 TDA235E5 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TDA235E0 | TDA21472 | TDA21536 | ISL99227 | MP8795 |
|---|---|---|---|---|---|---|
| Package | PG-MLGA-40 (6 x 6 x 0.8 mm³) | PG-MLGA-40 (same) | PQFN-40 (different family) | PQFN-40 (different family) | PQFN-40 (different family) | PQFN-40 (different family) |
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Renesas Electronics | Monolithic Power Systems |
| Architecture | Dual-phase | Dual-phase | Single-phase | Single-phase | Single-phase | Single-phase |
| Liquid Cooling Support | Yes | Yes | Limited | Limited | Yes | Yes |
| Telemetry | Current + Temperature | Current + Temperature | Current only | Current only | Current + Temperature | Current + Temperature |
| Target Topology | Vertical Power Delivery | Vertical Power Delivery | Lateral VR | Lateral VR | Multiphase VR | Multiphase VR |
主要差異化特點
- Highest power density dual-phase smart power stage in PG-MLGA-40 (對比ISL99227)
- Dual-phase integration eliminates 2x driver-FET parasitic loops (對比TDA21472)
- Liquid-cooling ready thermal package (對比MP8795)
設計說明
At 300 A peak per stage, power dissipation under load must be evaluated. Estimated: at VIN=12 V, VOUT=1.0 V, and 200 A continuous, the TDA235E5 dissipates approximately (12 - 1) × 200 = 2200 W per stage at 100% duty, although real dissipation is dominated by RDS(on) × I² losses in OptiMOS 6 FETs. Use the Infineon PG-MLGA-40 thermal model and attach a copper cold plate or large PCB copper pour (recommended 4+ oz inner copper). Liquid cooling is strongly recommended for sustained 300 A operation in AI accelerator rails.
The PG-MLGA-40 6 x 6 x 0.8 mm³ footprint requires a precisely designed land pattern per Infineon's package drawing. Use 4-layer or 6-layer PCB stackup with inner copper layers dedicated to GND and a high-current VIN/SW return. Keep the high-current loop between the high-side FET, inductor, and low-side FET under 2 mm² to minimize parasitic inductance. Place input bulk capacitors within 2 mm of the VIN pins and output capacitors within 5 mm of the SW nodes. The thermal pad must have at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) to inner copper layers.
For vertical power delivery (VPD) layouts where TDA235E5 mounts directly under the AI ASIC, route the SW nodes through high-density PCB vias into the processor substrate. Keep the analog ground (AGND) and power ground (PGND) separation short; use a single-point bridge near the controller's IMON input to avoid ground-loop noise corrupting current telemetry. Route the TMON/IMON analog traces as differential pairs with ground shielding if traces exceed 5 mm. Place the BOOT capacitors within 2 mm of the BOOT-SW pins with minimized loop area.
Do not operate TDA235E5 below the multiphase controller's minimum on-time, typically 50-100 ns, or the controller will skip pulses and induce audible/visible output voltage ripple. Ensure the Infineon AI rover controller is firmware-configured for the dual-phase mode of TDA235E5 - a single-phase configuration will only activate one of the two integrated phases, halving effective current capability. Always validate current sharing accuracy between the two integrated phases with a 4-channel oscilloscope during bring-up.
合規資訊
RoHS compliant per Infineon press release. Not AEC-Q100 qualified - TDA235E5 targets AI/data-center applications rather than automotive. Halogen-free and lead-free per Infineon policy.
