TPS53681RSBT - Dual 6+2/5+3 D-CAP+ Multiphase Buck Controller | TI
MPN： TPS53681RSBT ✓ 啟用中TPS53681RSBT 概覽
A buck controller is a switch-mode power-supply control IC that drives external MOSFETs or smart power stages to convert a higher DC input into a lower regulated DC output. A multiphase buck controller interleaves multiple converter phases to share load current, reduce input/output ripple, and spread heat across phases. Within the power-management hierarchy, the TPS53681 sits as buck controller -> DC-DC controller -> PMIC -> semiconductor, acting as the digital control brain for high-current VR rails rather than as a stand-alone regulator.
Key features include TI D-CAP+ adaptive on-time control that eliminates external RC compensation, full PMBus 1.3.1 compliance with telemetry and fault logging, output margining, adaptive voltage positioning, per-phase current sharing, and integrated NVM that stores user configuration without an external EEPROM. The 5x5 mm WQFN-40 footprint and TI NexFET smart power-stage pin compatibility keep the BOM small while supporting multi-hundred-ampere rails. The dual-channel architecture can be configured as 6+2 or 5+3 phases to support asymmetric CPU and GPU rails with independent VID tables.
The D-CAP+ control loop uses internal ripple injection and adaptive on-time, removing the compensation network required by traditional peak-current-mode controllers. Combined with TI NexFET smart power stages, the TPS53681 achieves high efficiency from sub-ampere sleep states to multi-hundred-ampere peak loads while integrating precision current sharing and per-phase fault protection. PMBus provides VID programming, output margining, and on-the-fly telemetry of VOUT, IOUT, temperature, and fault status for closed-loop platform management.
Typical applications include server and high-end desktop CPU core VRs supporting Intel VR13 and AMD SVI2 protocols, DDR4 and DDR5 memory VTT termination, workstation CPU and GPU power, base-station DSP and FPGA core rails, and PCIe auxiliary power. PMBus telemetry also makes it well suited to data-center PSUs and infrastructure platforms that require remote monitoring across the full operating temperature range.
When designing with this part, place decoupling capacitors within 2 mm of each PVCC and VCIN pin and follow TI NexFET layout guidelines for gate-drive return paths. Always configure NVM defaults using Fusion Digital Power Designer GUI before production ramp; mismatched PMBus addresses on parallel controllers can cause SMBus arbitration failures at start-up.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替換替代品，適用於 TPS53681RSBT — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： TPS53681RSBT （相同外形與佔位） — 差異在於 Non-Volatile Memory, Package, Phase Configuration, Topology, Number of Outputs.
TPS53681RSBR
✅ 直接替換📋 參考替代品（不在目錄中）
TPS53622RSBT
✅ 直接替換聯絡詢價
查看資料表 →TPS53681RSBT 最大額定值與電氣特性
| 拓撲 | Multiphase synchronous buck controller |
| 輸出數量 | 2 (dual-channel) |
| Phase Configuration | 6+2 or 5+3 phases |
| Control Method | D-CAP+ adaptive on-time |
| VCC/VDD Input Voltage | 4.5 V to 17 V |
| PVCC Operating Voltage | Up to 28 V |
| 輸出電壓範圍 | 0.25 V to 5 V |
| Per-Rail Output Current (typical) | >100 A |
| Per-Rail Output Current (peak) | Up to 300 A |
| PMBus Interface | PMBus 1.3.1 compliant |
| Non-Volatile Memory | Integrated NVM for configuration |
| 工作接面溫度 | -40 C to +125 C |
| 封裝 | 40-pin WQFN (RSB), 5x5 mm |
| 安裝類型 | Surface Mount |
| Compatible Power Stage | TI NexFET smart power stages |
| MSL 等級 | 2 (per JEDEC J-STD-020) |
| RoHS 狀態 | Compliant |
TPS53681RSBT 腳位配置
| 腳位 1 | VCC — Analog/digital supply input (4.5-17 V) |
| 腳位 2 | VDD — Internal logic supply input |
| 腳位 3 | PVCC — Gate-drive supply (up to 28 V) |
| 腳位 4 | BOOT1 — Bootstrap for channel 1 high-side gate |
| 腳位 5 | UGATE1 — Channel 1 high-side gate drive to NexFET |
| 腳位 6 | LGATE1 — Channel 1 low-side gate drive to NexFET |
| 腳位 7 | FB1 — Channel 1 output voltage feedback |
| 腳位 8 | COMP1 — Channel 1 D-CAP+ compensation node |
| 腳位 9 | EN1 — Channel 1 enable input |
| 腳位 10 | SDA — PMBus serial data |
| 腳位 11 | SCL — PMBus serial clock |
| 腳位 12 | ADDR — PMBus address selection |
| 腳位 13 | GND — Analog ground |
| 腳位 14 | PGND1 — Channel 1 power ground |
| 腳位 15 | BOOT2 — Bootstrap for channel 2 high-side gate |
| 腳位 16 | UGATE2 — Channel 2 high-side gate drive to NexFET |
| 腳位 17 | LGATE2 — Channel 2 low-side gate drive to NexFET |
| 腳位 18 | FB2 — Channel 2 output voltage feedback |
| 腳位 19 | COMP2 — Channel 2 D-CAP+ compensation node |
| 腳位 20 | EN2 — Channel 2 enable input |
| 腳位 21 | VCIN — Voltage conversion in supply |
| 腳位 22 | NC — Not connected (per datasheet) |
| 腳位 23 | NC — Not connected (per datasheet) |
| 腳位 24 | NC — Not connected (per datasheet) |
| 腳位 25 | NC — Not connected (per datasheet) |
| 腳位 26 | NC — Not connected (per datasheet) |
| 腳位 27 | NC — Not connected (per datasheet) |
| 腳位 28 | NC — Not connected (per datasheet) |
| 腳位 29 | NC — Not connected (per datasheet) |
| 腳位 30 | NC — Not connected (per datasheet) |
| 腳位 31 | NC — Not connected (per datasheet) |
| 腳位 32 | NC — Not connected (per datasheet) |
| 腳位 33 | NC — Not connected (per datasheet) |
| 腳位 34 | NC — Not connected (per datasheet) |
| 腳位 35 | NC — Not connected (per datasheet) |
| 腳位 36 | NC — Not connected (per datasheet) |
| 腳位 37 | NC — Not connected (per datasheet) |
| 腳位 38 | NC — Not connected (per datasheet) |
| 腳位 39 | NC — Not connected (per datasheet) |
| 腳位 40 | PGND2 — Channel 2 power ground |
典型應用
TPS53681RSBT 適用於 6 應用s: Server CPU Core VR (Intel VR13 / AMD SVI2), DDR4 / DDR5 Memory VTT Termination, Workstation GPU and CPU VR, Base-Station DSP and FPGA Core Rails, PCIe Card Auxiliary Power, Data-Center PSU and VRM Telemetry Backbone.
Server CPU Core VR (Intel VR13 / AMD SVI2)
The TPS53681RSBT's dual-channel 6+2 or 5+3 phase architecture and 0.25 V to 5 V output range make it ideal for server CPU core VR rails supporting Intel VR13 and AMD SVI2 protocols. Channel A drives the 6-phase or 5-phase CPU core at greater than 100 A typical and up to 300 A peak during turbo transients, while channel B drives the 2-phase or 3-phase GPU or system agent rail at lower currents. PMBus 1.3.1 telemetry delivers on-the-fly VOUT, IOUT, and temperature monitoring for platform management, and the integrated NVM stores the boot configuration so the VR comes up without an external EEPROM. Designers pair the TPS53681 with TI CSD95490 or CSD97395 NexFET smart power stages and 220 nH inductors to hit greater than 90 percent peak efficiency at 1 V output.
推薦
DDR4 / DDR5 Memory VTT Termination
For DDR4 and DDR5 memory VTT termination rails on server and workstation motherboards, the TPS53681RSBT provides a second independent step-down output at the half-VDDQ voltage required by JEDEC memory termination. Channel B can be configured as a 2-phase or 3-phase VTT rail at 0.6 V to 1.2 V typical, tracking the VDDQ rail through PMBus write commands. The D-CAP+ adaptive on-time control eliminates compensation components, and the WQFN-40 footprint stays compact next to DIMM sockets. TI NexFET CSD95490 power stages deliver the high peak current demanded by DDR burst writes with low thermal rise.
推薦
Workstation GPU and CPU VR
Workstation boards with separate CPU and GPU packages benefit from the TPS53681RSBT's dual-channel independent VID control. Channel A drives the 6-phase CPU core while channel B drives the 3-phase or 2-phase GPU rail at independent voltages - the TI design tool lets designers load separate SVI2 VID tables into NVM for asymmetric power states. Per-phase current sharing balances thermal load across power stages, enabling sustained 100 A per rail in thermally constrained workstation chassis. Adaptive voltage positioning flattens the load line to reduce bulk output capacitance requirements versus analog controllers.
推薦
Base-Station DSP and FPGA Core Rails
Telecom base-station DSP cards and FPGA accelerator boards use the TPS53681RSBT to generate the sub-1 V core voltage demanded by modern DSP and FPGA silicon such as TI KeyStone II and Xilinx Versal. The 4.5 V to 17 V VCC input accepts -48 V telecom bus intermediate voltages (after front-end conversion to 12 V), and PMBus 1.3.1 telemetry reports VR status back to the base-station shelf controller over I2C. Operating junction temperature of -40 C to +125 C covers outdoor and central-office deployments. The WQFN-40 5x5 mm package dissipates controller heat efficiently without external heatsinking.
推薦
PCIe Card Auxiliary Power
High-end PCIe accelerator cards (AI cards, FPGA cards, GPU compute cards) draw auxiliary 12 V or 8-pin power beyond the slot budget. The TPS53681RSBT generates on-card core voltages from this auxiliary input, driving two independent rails - typically a 0.85 V FPGA core and a 1.2 V auxiliary rail. The PMBus interface lets the host BIOS or BMC poll VOUT, IOUT, and temperature for thermal throttling decisions, while the integrated NVM stores default boot VID without an external EEPROM. Designers select TI NexFET CSD95490 or CSD97395 stages based on rail current.
推薦
Data-Center PSU and VRM Telemetry Backbone
In data-center 48 V intermediate bus and 12 V bus architectures, the TPS53681RSBT serves as the VRM digital brain with PMBus 1.3.1 telemetry that integrates with Redfish or IPMI management interfaces through an intermediate BMC. The dual-channel design can drive one CPU VR and one network-ASIC VR on the same OCP server card, reducing component count. The on-chip NVM stores per-platform default boot configurations, allowing the same TPS53681 firmware image to support multiple server SKUs. Operating across -40 C to +125 C junction covers cold-aisle intake temperatures to hot-aisle exhaust.
推薦
推薦產品摘要
工程參考資料，適用於 TPS53681RSBT — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TPS53681RSBR | TPS53622RSBT | TPS53632GRSMT |
|---|---|---|---|---|
| Package | WQFN-40 (RSB) 5x5 mm | WQFN-40 (RSB) 5x5 mm - same | WQFN-40 (RSB) 5x5 mm - same | WQFN-32 (RSM) - smaller |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Number of Outputs | 2 (dual-channel) | 2 (dual-channel) | 1 (single-rail) | 1 (single-rail) |
| Phase Configuration | 6+2 or 5+3 | 6+2 or 5+3 | 4+1 or 3+2 | 3+1 or 2+2 |
| VCC Input Voltage | 4.5 V to 17 V | 4.5 V to 17 V | 4.5 V to 17 V | 4.5 V to 17 V |
| Output Voltage Range | 0.25 V to 5 V | 0.25 V to 5 V | 0.25 V to 5 V | 0.5 V to 3.3 V |
| Per-Rail Output Current (peak) | Up to 300 A | Up to 300 A | Up to 200 A | Up to 100 A |
| Control Method | D-CAP+ adaptive on-time | D-CAP+ adaptive on-time | D-CAP+ adaptive on-time | D-CAP |
| PMBus Interface | PMBus 1.3.1 | PMBus 1.3.1 | PMBus 1.3.1 | PMBus 1.2 |
主要差異化特點
- Dual-channel 6+2 or 5+3 phase architecture in a single controller (對比TPS53622RSBT)
- Integrated NVM stores configuration without external EEPROM (對比TPS53632GRSMT)
- Full PMBus 1.3.1 telemetry vs PMBus 1.2 on older families (對比TPS53632GRSMT)
設計說明
Place decoupling capacitors within 2 mm of each PVCC, VCC, and VCIN pin. Use a 1 uF X7R ceramic bypass on each PVCC pair and a 0.1 uF X7R on VCC/VDD. Route the BOOT-UGATE-LGATE-PGND traces as a tight loop with the corresponding NexFET smart power stage to minimize gate-drive parasitic inductance; long traces can cause shoot-through and degrade efficiency.
The WQFN-40 (RSB) 5x5 mm package dissipates controller losses through the central exposed pad; solder this pad to a continuous copper pour with at least 25 thermal vias to the inner ground plane. Estimated: at 4.5 V VCC input and 0.85 V/100 A output per channel, controller losses are below 1 W and do not require an external heatsink. Total system losses (controller plus NexFET stages) typically range from 8 W to 14 W at full load.
Always configure NVM defaults using TI Fusion Digital Power Designer GUI before production ramp; mismatched PMBus addresses on parallel controllers can cause SMBus arbitration failures at startup. Verify the PMBus ADDR pin resistor divider matches the desired slave address - the controller reads ADDR at power-up and uses it for all subsequent transactions. Do not apply VIN above 17 V on VCC or 28 V on PVCC, as the internal LDO will latch up.
Follow TI NexFET layout guidelines for gate-drive return paths. Place the channel-1 and channel-2 NexFET power stages symmetrically around the controller to balance PCB trace lengths, and use a star-ground topology where each phase's PGND returns to the controller before connecting to the system ground. Avoid routing FB traces near switching nodes - capacitive coupling can inject ripple into the D-CAP+ feedback path.
合規資訊
RoHS and REACH compliant per TI product page. MSL Level 2 per JEDEC J-STD-020. Not AEC-Q100 qualified - choose TPS53681-Q1 suffix variant for automotive. Halogen-free per TI 2009 eco-design declaration.
